False Path Constraints

[Altera_Forum]

Hi, 

 I have two clocks coming from two different clock sources (ClkSrcA, ClkSrcB), going to two different PLLs (PLLA, PLLB), generating two clocks (ClkA, ClkB).   In the design data is transferred from ClkA registers to ClkB registers.  1) Would I need to set a FALSE PATH between them?  2) Doesn't TimeQuest know that these clocks are from two different PLLs and hence are not synchronous?   Thanks

[Altera_Forum]

You shouldn't set false path. Instead you should transfer data safely across clock domains. It is your responsibility, not that of TimeQuest

[Altera_Forum]

You need to do both in fact ;) 

By default Timequest assumes that you are not doing safe cross between domains, so if you have two different clocks at two different frequencies, and data going between them, you'll probably have messages from Timequest saying that the timing constraints are not met. Once you are sure you added enough logic to cross safely from one clock domain to the other, you can add some sdc commands for Timequest. You can either define false path or put the clocks in different groups.