timing requirements not met, but design works

[Altera_Forum]

Hello everybody, 

 I have been testing my system and everything seems to be ok.  I am processing one image, and the output is what I expected.  However the classic timing analyzer said me that the "Total number of failed paths is 1069".  What does it means? I am using one PLL that receives a 24MHz signal, and generate one 160MHz clock. (I suppose that because I am using this PLL, Quartus knows about the frequency)  I am using Cyclone 2 speed grade 8.  Thank you.

[Altera_Forum]

--- Quote Start ---  What does it means?  --- Quote End ---   Assuming the timing analysis parameters are basically correctly describing your design, it means, your design may operate incorrect under particular conditions, e.g. higher temperature, supply voltage at the lower tolerance band, individual device variations. Each path failure should be inspected and corrected somehow.  You may have a lock at the negative slack reported for failed paths to judge the respective severity. If it's rather low, e.g. below 0.5 ns, the timing failure most likely won't show up. But it's not O.K. anyway.   A general method to take the edge of a critical timing is adding pipelining registers to a data path, if applicable. As a first step, you should try to understand where the timing bottleneck of your design is located.

[Altera_Forum]

Hello Guys, 

 I optimized my code, and know the slack is 0.429 ns, uff. (positive).  And the total failed paths is 0 Zeroooooo. UIPI.   I have a question ::confused:  what means the message in the field:  ACTUAL TIME= "Restricted to 163.03 MHz ( period = 6.134 ns )",    BEFORE the timing analyzer had given me a number: Actual Time 179.08 MHz ( period = 5.584 ns ), I made some modifications, and now it does not give me a number.   Thank you.  DABG