AND vs XOR gate

[Altera_Forum]

Im sorry if my post doesnt belong to here. Just a short question: 

 Which one is larger in term of implementation?  AND gate or XOR gate ?  thanks

[Altera_Forum]

Well since you are asking the question in an FPGA forum, the answer is: 

"They are the same.". Both fit inside a single ALUT.  Now if the question were about implementing the operation in silicon. The XOR gate would have a higher transition count.  A XOR gate equates to: A+B & !(A&B).  Jake

[Altera_Forum]

hmmm...say im looking into their operation unit time. hence one XOR require longer time in comparison to AND then?

[Altera_Forum]

Why are you comparing the speeds of the two functions? They are two different operations. You must be looking at some larger operation and trying to decide how to implement it. In which case, you should compare the speed of the larger operations and not these simple logic operations. 

 For example: given reg [15:0] a; reg [15:0] b; reg res;  then: res <= !(a^b)  is faster than but consumes one more LUT than: res <= (a == b);  Jake

[Altera_Forum]

yes..something like that. actually Im trying to determine the critical path and the implementation size of a given arithmetic circuit which consist of AND gate and XOR gate.

[Altera_Forum]

Hi, 

 Use one project with a switch(constant or generic) to instantiate either case of the arithmetic circuit. Compile each case and see report. It will tell you per device what you are after.

[Altera_Forum]

FPGAs use lookup tables. The lookup tables are programmed with the output of the logic you are implementing. For a two input AND or XOR gate this is what you can expect the LUT to look like: 

  address AND XOR  0 0 0  1 0 1  2 0 1  3 1 0  The address is just your two inputs grouped together. In other words if you have y = A & B, then the address is just the bits A B grouped together. These form the address input of the lookup table and the data that comes out of the lookup table is signal 'y'.  Because an AND or XOR gate both fit into a single lookup table there shouldn't be any difference in the operation speed since this is determined by how fast the data in the LUT can be accessed (amongst other things like pipelining, routing delays, etc...)

[Altera_Forum]

The explanation of BadOmen is perfect. I will add that I believe the idea also includes how math functions are implemented in either case.

[Altera_Forum]

Thank you very much for the replies. So what about implementation in ASIC? will it be the same like FPGA where both XOR and AND are fitted into one ALUT?

[Altera_Forum]

Hi, 

 ASIC design is different world from ours(the fpga). Though it is based on RTL usually. You will need to refer to their literature but it certainly does not use lut. Instead it is based on standard cells. Each vendor provides a library of these cells.   The cells are designed at transistor level to directly implement some logical functions e.g. and,or,nand etc as well as registers/flips.   The vendors are free to choose and design their lowest level functions in whatever way. The library or the user can combine these cells to produce higher level functions.   Si, I believe, the answer depends on the cells you choose.

[Altera_Forum]

In an ASIC if I remember correctly the XOR gate will be larger transistor wise than an AND gate. Like Kaz said, ASICs don't use lookup tables to implement logic since they are not designed to be reprogrammed. When you program an FPGA one of the things you are doing is programming the lookup tables to implement your combinatorial logic. In an ASIC this logic are just static transistors which keeps the size and power down.