Quartus equivalent to XST attribute rom_extract

[Altera_Forum]

Hello, 

 I am working on a design that should use some ROM blocks. I know that on Virtex4 you can use rom_extract attribute to pack a component that uses a large WITH...SELECT statement into ROM, but I have yet to find an equivalent that works on StratixII.   I read in the recommended HDL coding style chapter that by writing a CASE statement it would be packed into ROM, but each ROM function has to meet a minimum size requirement to be inferred and placed into memory. Does anyone know what is this minimum size requirement?  Thx

[Altera_Forum]

I'm not sure on the actual size. What you can do is apply the "allow_any_rom_size_for recognition" assignment either to your module or the entire design. 

 To do it just for the module, use the assignment editor. To apply it to the whole design; Assignments->Settings->Analysis & Synthesis Settings->Allow Any ROM Size for Recognition.  Jake

[Altera_Forum]

Thank you for the quick reply Jake! 

 Your advice was very usefull. When I set the "allow_any_rom_size_for_recognition" ON the compiler generated an altsyncram megafunction for the component I wanted. Unfortunately it generated the same megafunction for other components that would have been better implemented in logic. When I tried to used the assignment editor to assign only the desired component to RAM the synthesis summary was exactly the same as the one that had not used ROM at all. Also I was not able to find any messages saying that altsyncram megafunction was inferred. On the other hand I found a warning saying warning: feature logiclock is not available with your current license. Could this be the reason why the assignment from the Assignment Editor had no effect?  After a bit of searching I found an interesting thing in the QuartusII Handbook, Integrated Synthesis: there is actually a VHDL attribute called romstyle that should infer ROM when used in describing a component, unfortunately it has no effect when I compile the design. Could this also be because of the previous warning?  Benny

[Altera_Forum]

I don't think the "LogicLock" warning has anything to do with the issue at hand. LogicLock is a feature that Quartus offers to allow you to physically constrain the placement of logic to specific areas of the chip. I don't suppose you could post your design? I wouldn't mind playing with it to see what can be done. If not, I'll see if I can produce something similar. 

 Jake

[Altera_Forum]

Unfortunately the design is to large to be posted here (over 51K characters). If you want I can send you an e-mail with the design attached, or you can generate it by the downloading an SVN version of the FloPoCo project: 

 svn checkout svn://scm.gforge.inria.fr/svn/flopocoand writing the command:  #./flopoco -frequency=200 FPLog 8 23 7The design is generated from FloPoCo arithmetic core generator and represents a floating point logarithm on simple precision FP numbers. The target frequency is 200MHz on Virtex4, I want to optimize it for StratixII to run at the same frequency and use fewer logic resources than the default implementation. The first step would be to substitute the rom_extract attribute in the architecture of the IntIntKCM_8_93032640 component by something that quartus recognizes. That would place KCMFirstTable_6_33 component into ROM memory.   Thx a lot for helping, I really appreciate it.  Benny

[Altera_Forum]

Regarding the problem of setting Quartus logic options as "allow_any_rom_size" for individual design entities, this can be achieved by synthesis attributes in HDL code. 

 See the chapter "Using altera_attribute to Set Quartus II Logic Options" in Quartus Software Handbook.   Also the Assignment Editor Tool allows to set this option to design entities.

[Altera_Forum]

Hello, 

 Problem solved by using altera_attribute. Thanks a lot FvM! This is exactly what I needed.

[Altera_Forum]

I'm very confused as to why the assignment made in the assignment editor did not work. This is exactly the same thing as using "altera_attribute" within the code. Did you make the assignment on a different entity when doing through the assignment editor vs. through the code? 

 Jake

[Altera_Forum]

I'm sure, it works as well. But I would prefer synthesis attributes in HDL code in this case, because they are self-documenting and ported with the HDL code, when re-using a design.

[Altera_Forum]

--- Quote Start ---  I'm very confused as to why the assignment made in the assignment editor did not work. This is exactly the same thing as using "altera_attribute" within the code. Did you make the assignment on a different entity when doing through the assignment editor vs. through the code?  Jake  --- Quote End ---    Hi,  It was the first time when I was using the assignment editor so that was probably the case. I'm not so good at using the GUI, but nevertheless your advice also helped. Thanks again.  Benny