High Speed I/O pin Locking

[Altera_Forum]

Hello, 

 I am trying to port a design on Arria II GX FPGA. I want to use the high speed I/O pins that this FPGA has. However using Quartus II v9.0 I am unable to do so. Whenever I try to lock any pin/signal on this bank (QL0 bank for high speed I/O), there is an error message for I/O standards used and sometimes gives "invalid pi allocation for this bank". Can anyone please let me know how do I do the pin assignments for the high speed I/Os in Quartus. Is there anything I am missing, any particular settings or there is anything in particular these I/Os need.  Regards, Anirban Moitra

[Altera_Forum]

Hi Anirban, 

 While I don't work on this part of Quartus II myself, I asked someone who does, and he said the QL0 pins are only useable when attached to a transceiver - in other words, you can't use them for regular IO.  I would suggest you read over the Arria II GX handbook section on IOs, available at http://www.altera.com/literature/hb/arria-ii-gx/aiigx_5v1_02.pdf. Hopefully that will help resolve your issues.  Cheers, Adrian Ludwin Altera Corp.