Using differental input buffer as comparator

[Altera_Forum]

Hi, 

I'm designing a system using comparators to signalize analog signals, I wanna know that can I use the differental input pins on FPGA as comparators? If it is possible, the PCB will be smaller and maybe faster? Anyone has some idears? Thanks

[Altera_Forum]

I suppose you could if the conditions were right. You would be restricted to the limitations of the device as far as the voltage levels. 

 Look at the datasheet for the device you intend to use. For example, here is the datasheet for Stratix IV: http://www.altera.com/literature/hb/stratix-iv/stx4_5v4_01.pdf  Page 1-10 gives the differential IO standards specifications. So for example, if you look at LVDS, the minimum Vid (differential input voltage) is 10mV. Anything less than that and it would not be able to "compare". Also note that you must obey the Vcm (common mode voltage) of the device. This is where I think the usefulness as a comparator breaks down.  Jake

[Altera_Forum]

thanks,i've see the data sheet, and the working condition is within the diff io feature. i'm going to test the differental io pins by some analog signals like sin or triangle, to see if it works.

[Altera_Forum]

there is an IEEE paper on abusing FPGA I/O as sigma delta converters: 

 http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1328388

[Altera_Forum]

that was kind of a half baked thought. i should add, you may be able to get some ideas from the IEEE paper to use the I/O as a comparator rather than a full ADC.