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We are using a DE3 board running TSE + NIOS II, and a HSMC-NET Marvell PHY daughter card. The simple socket server design example works.
However, we do not want to use the RTOS or Interniche stack so I need to replace the Altera example drivers with more compact drivers. - My SGDMA drivers are functional - Ethernet Rx works. - If MAC loopback is enabled Ethernet Tx looping back to the Rx works. - If MAC loopback is disabled Wireshark on the PC does not receive any packets from the embedded board. (Over a dedicated 100Mbit ethernet cable). Can anyone suggest why the packets are not being transmitted out of the PHY? Thanks, Paul.Link Copied
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You should use a SignalTap probe on the MII interface to check if anything is sent out to the Phy.
Check also that you are sending at the correct speed (i.e. that the speed between the MAC and the PHY is the same than the one that the PHY negotiated on the cable), and that the timing constraints on the interface to the PHY are met.- Mark as New
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There's a Superloop example available on the NiosWiki which might suit your needs better.
http://nioswiki.com/index.php?title=exampledesigns/superloopsimplesocketserverplus Cheers, - Brendan
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