Cyclone III-120: M9K read, write failure

[Altera_Forum]

Hi, 

In our design I have a custom memory controller connected to the Avalon MM bus, with one Avalon MM interface, and at the other side of the controller I have four instantiations of 512x32b memory each. At the Avalon side the memory can be addressed from 0x20000 upto 0x21ffc. If 0x20000 is addressed memory 1 is written or read, if 0x20004 is addressed memory 2 is written or read, if 0x20008 is addressed memory 3 is written or read etcetera ... In simulation everything is okay, I can read and write all memories, but at the target it is impossible to write and read memory 3, all the other memories are okay. If I look with signal tap at memory 3 I see the write with the correct data, I also see the read with incorrect data. I always read 0x00000000, independent of what I write. If I look into the RTL Netlist I see that all memories are connected as expected.  Some info: target is the Cyclone III 120, memory is not synthesized away, 80% of the memory blocks are in use, 45% of LE are occupied.  Are there known issues with (some) M9K blocks? Does someone recognize this behaviour? All suggestions for analysis are welcome!  Kind regards, Bert

[Altera_Forum]

Hi Bert. 

 I've uses the Cyclone III's since their release, (Mostly the 3C25, 3C40, 3C55, and 3C80)  I have never seen the issue you have described. You stated you can see the Writes happen and the Read's fail, Are you tapping right at the port of the ram instance? My thought is either a clock, write enable or read enable is not connected properly. You would think these issue would show up in simulation however.  If it was a bad M9k, you would think the problem would move around from synthesis run to synthesis run.  If you post the code snippet, I'm sure someone can be of more help.

[Altera_Forum]

Hi Anakha, 

 Thank you for your reply. i agree with you that the failure should move with the several synthesis runs I did, but the failure is always on the same memory block, so I also guess it has nothing to do with which memory block is used and I also asume for now that there is no timing issue, because the reports do not report an timing error. But, until today I still have the error and made some extra logs with signal tap. three instantiations, three identical timing diagrams, but one memory block fails ... I keep on searching for this interesting bevaiour.  Bye, Bert

[Altera_Forum]

Another issue is it may be related to the particular version of Quartus you are using for synthesis. 

 Are you using the latest (Quartus 9.0 SP2)  Pete

[Altera_Forum]

Hi Pete 

 Yes, although the design is initially made in 8.1, I did an upgrade to 9.0SP1, so not 9.0Sp2. As far as I can see the timing analysis bug is already solved in SP1, but I will get SP2 and see what happens.  Thanks! Bert

[Altera_Forum]

Hi 

 I have changed the memory structure from three memory block behind on Avalon MM interface to one larger memory block. After changing the memory controller I did some tests with succes.   It works, but still can not find any good reason why the previous design didn't work correctly. As I said, I measure the same timing diagrams on three memory blocks, but one refuse to remember what I a write.    Bye Bert