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I'm doing a circuit with a Cyclone III, it expects inputs from comparators that are 5V powered. What is a cheap, low latency (less than 100ns at least) solution to shift that to 3.3V to keep the FPGA happy?
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You can use 5V-tolerant buffers, such as the 74lvc241 (http://www.standardics.nxp.com/products/lvc/datasheet/74lvc241a.pdf).
Having comparators with open collector outputs is also an alternative.- Mark as New
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100ns is rather slow. A resistive divider can do.
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