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PLL Auto Phase Adjust (Source Sync Outputs)

Altera_Forum
Honored Contributor II
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Hello all, 

 

I am trying to create an S-RAM controller ony my C3STK board, and I am attempting to achieve the highest possible transfer speed (200MHz for the S-RAM device). 

 

For this, I am trying to constrain the S-RAM inputs in relation to the external S-RAM clock driven by the Cyclone III. I have configured setup/hold constraints in TimeQuest for the pins driving the SRAM addres/data/control bus in relation to its clock signal. I have used the Source Synchronous Interface application note from Altera to achieve this. 

 

I am using the PLL to generate the internal 200MHz system clock, and a second dedicated clock that drives the S-RAM clock pin. According to the app-note this is a suitable way to meet timing constraints as the PLL "should" and could adjust the phase of this dedicated clock pin to meet the constraints. The PLL is set to use the Zero-Delay buffer compensation for the clock output that drives the external S-RAM clock. 

 

However, I have noticed that the fitter does not re-adjust the phase setting for my PLL and I have to use the timing analyzer to verify if constraints are met and if not, adjust the phase myself in the PLL megafunction to get it to work. 

 

Is there any way to instruct the compiler/fitter to auto-adjust the phase for the S-RAM clock as needed to meet the timing constraints (and backannotate it to the design file)? 

 

Much appreciated, 

Arno.
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Altera_Forum
Honored Contributor II
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Well, looks like I'm not going to need an auto phase adjust at all. I've been optimizing the circuit a bit and inserted a DDIO element as an S-RAM clock repeater to have the fullspeed clock originate from an IOB register as well. With a 270 degrees phase shift for the dedicated PLL source on 200MHz, the S-RAM controller works perfectly now ;) 

 

It is able to interact with the S-RAM on the starter kit at the full 200MHz speed with plenty slack left for the Tsu/Th requirements of the S-RAM. There are no delay cycles, except that for going from a read to a write there will be an extra dead cycle to avoid bus drive contention between the Cyclone and the S-RAM.
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