Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20704 Discussions

ZDB Mode - How to verify correct routing / resource usage

Altera_Forum
Honored Contributor II
‎06-13-2017 07:48 AM
1,102 Views

Hi all, 

 

how can I verify that my output clocks are routed directly from the PLL to the clock output pin and not through logic or clock networks? I want to make sure that I'm using zero-delay buffer mode correctly. 

 

Many thanks in advance! 

 

Regards, sö
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.