sof2flash

Altera_Forum · ‎09-09-2009

i want to create a flash file with the nios2 shell the problem is, if i use sof2flash it creates a EPCS128 file but i have a EPCS16 file:

$ sof2flash --epcs --input=FPGA.sof --output=FPGA.flash
Info: *******************************************************************
Info: Running Quartus II Convert_programming_file
Info: Command: quartus_cpf --no_banner --convert --device=EPCS128 --option=FPGA.opt FPGA.sof FPGA.pof
Info: Using INI file c:/altera/90/quartus/bin/quartus.ini
Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 78 megabytes
    Info: Processing ended: Wed Sep 09 12:56:12 2009
    Info: Elapsed time: 00:00:09
    Info: Total CPU time (on all processors): 00:00:04
Info: *******************************************************************
Info: Running Quartus II Convert_programming_file
Info: Command: quartus_cpf --no_banner --convert FPGA.pof FPGA.rpd
Info: Using INI file c:/altera/90/quartus/bin/quartus.ini
Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 72 megabytes
    Info: Processing ended: Wed Sep 09 12:56:24 2009
    Info: Elapsed time: 00:00:12
    Info: Total CPU time (on all processors): 00:00:05
$

is there a way to change that?

Altera_Forum · ‎09-09-2009

That doesn't matter. As has been stated before, on this Forum and the Nios Forum, EPCS devices are just OEMed serial (SPI) flash devices.

Are you having other issues that caused you to post this topic thread?

Best Regards,

- Ura

Altera_Forum · ‎09-10-2009

if i create a *.jic file using quartus i can flash my epcs.

if i try to flash the epcs using the nios2 shell i get an error:

$ sof2flash --epcs --input=FPGA.sof --output=FPGA.flash
Info: *******************************************************************
Info: Running Quartus II Convert_programming_file
Info: Command: quartus_cpf --no_banner --convert --device=EPCS128 --option=FPGA.
opt FPGA.sof FPGA.pof
Info: Using INI file c:/altera/90/quartus/bin/quartus.ini
Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 78 megabytes
    Info: Processing ended: Thu Sep 10 07:34:48 2009
    Info: Elapsed time: 00:00:09
    Info: Total CPU time (on all processors): 00:00:04
Info: *******************************************************************
Info: Running Quartus II Convert_programming_file
Info: Command: quartus_cpf --no_banner --convert FPGA.pof FPGA.rpd
Info: Using INI file c:/altera/90/quartus/bin/quartus.ini
Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 72 megabytes
    Info: Processing ended: Thu Sep 10 07:35:00 2009
    Info: Elapsed time: 00:00:11
    Info: Total CPU time (on all processors): 00:00:05
$ nios2-flash-programmer --epcs --base=0x2000 --instance=1 FPGA.flash
Using cable "USB-Blaster ", device 1, instance 0x01
Resetting and pausing target processor: OK
No EPCS registers found: tried looking at addresses
     0x00002000, 0x00002100, 0x00002200, 0x00002300 and 0x00002400
Leaving target processor paused

and yes my epcs is at that address:

#define EPCS_CONTROLLER_NAME "/dev/epcs_controller"# define EPCS_CONTROLLER_TYPE "altera_avalon_epcs_flash_controller"# define EPCS_CONTROLLER_BASE 0x00002000

any ideas? :)

Altera_Forum · ‎09-10-2009

Which device are you using? Check to make sure you've got the configuration pins set up correctly in the device settings

Assignments->Device->Device And Pin Options->Dual-Purpose Pins

Jake

Altera_Forum · ‎09-10-2009

i can't see the epcs pins there.

why do they have to be regular I/O pins?

doesn't the problem say that there are no epcs regs at the specified address?

Altera_Forum · ‎09-10-2009

Are you sure you've got the right FPGA image programmed into the FPGA and is your design meeting timing requirements?

jake

Altera_Forum · ‎09-10-2009

An EPCS device is really just a SPI (serial) flash. So, the epcs_controller, in your SOPC Builder system, acts as a SPI master talking to the SPI slave (serial flash EPCS device).

Depending upon your device, the SPI signals are either connected automatically for you or you have to do it at the top-level of your design.

When connected automatically, you have to ensure that your Dual Purpose pins settings will allow the ASMI/SPI signals to function properly...which is what Jake was referring to.

Cheers, and Good luck!

- Ura

Altera_Forum · ‎09-10-2009

--- Quote Start ---

Are you sure you've got the right FPGA image programmed into the FPGA and is your design meeting timing requirements?

jake

--- Quote End ---

I'm runnig uClinux on that image and normal IDE stuff so timing requirements are fine.

I'm able to flash the EPCS using the programmer, doesn't that mean my pins are fine or is the programmer using other ways to transmit data ? :eek:

Altera_Forum · ‎09-10-2009

The JIC method downloads it's own firmware image into the part then uses JTAG to program the flash indirectly. The nios2-programmer method depends on your design. It expects that your design is loaded. It then uses JTAG commands to access the flash through your design.

Jake