Low Voltage Cyclone III Configuration

[Altera_Forum]

I'm doing a low voltage (1.8V) design and would like to find a configuration EEPROM to interface to my Cyclone III. Is such a part available?

[Altera_Forum]

A search on Digikey turns up thousands of EEPROMs that will run at 1.8V. For example the M24128-BR from STMicro. Just do a search and enter your criteria. 

 Jake

[Altera_Forum]

Yes, thanks, I should have stated my question more clearly. The SST25WF040 from SST is a 4Mbit device that could substitute for the EPCS4. But will it "talk" to the FPGA in an AS configuration mode correctly. This reflects my ignorance of the protocol used between the FPGA and configuration device.

[Altera_Forum]

Ah, I see. Well I can't answer the question specifically regarding the SST25WF040. I can say that I have a 1.8V Stratix II GX design that is interfaced directly to an EPCS64 device (which is supposed to be a no-no). and it works beautifully. 

 Anybody else have any recommendations regarding the SST part?  Jake

[Altera_Forum]

Interesting. Did you run the I/O bank which contains the AS configuration signals (DCLK, DATA0, etc.) and the JTAG signals at 1.8V? How about the I/O bank which contains the MSEL signals?

[Altera_Forum]

DCLK, DATA0, ASDO and nCSO are all on the same bank and powered by 1.8V. The MSEL pins are on another bank which also has VCCIO of 1.8V. However, on Stratix II GX, MSEL pins are externally tied to GND or VCCPD. 

 Jake

[Altera_Forum]

It looks like VCCPD is 3.3V for the Stratix II. So you had VCCIO for the MSEL pins at 1.8V, but tied them to 3.3V? Is this OK? Did you use series resistors? 

 Does JTAG configure OK if the VCCIO for those pins is 1.8V?

[Altera_Forum]

From the Stratix II GX pin connection guidelines: 

  --- Quote Start ---  These pins are internally connected through a 5-kΩ resistor to GND. Do not leave these pins floating. When these pins are unused, connect them to GND. Depending on the configuration scheme used, these pins should be tied directly to VCCPD or GND. Refer to the Configuring Stratix II and Stratix II GX Devices chapter in volume 1 of the Configuration Handbook. If only JTAG configuration is used, connect these pins to ground.  --- Quote End ---    And from the Stratix II GX User's Guide: The configuration scheme is selected by driving the Stratix II or Stratix II GX device MSEL pins either high or low as shown in Table 13–1.   --- Quote Start ---  The MSEL pins are powered by the VCCIO power supply of the bank they reside in. The MSEL[3..0] pins have 9-kΩ internal pull-down resistors that are always active. During power-on reset (POR) and during reconfiguration, the MSEL pins have to be at LVTTL VIL and VIH levels to be considered a logic low and logic high. 1 To avoid any problems with detecting an incorrect configuration scheme, hard-wire the MSEL[] pins to VCCPD and GND, without any pull-up or pull-down resistors. Do not drive the MSEL[] pins by a microprocessor or another device.  --- Quote End ---    However, I did disregard this council somewhat as I wired them too a DIP switch that when closed pulled them directly to 3.3V and when open pulled them through 10K resistors to ground.  Jake

[Altera_Forum]

You've been very helpful, thanks.

[Altera_Forum]

The only real problem is the VIH parameter on the flash part. For example, the EPCS64 datasheet claims a VIHmin of 0.6 * VCC. So if VCC for the flash is 3.3V, I should provide at least 1.98V on ASDO (which I obviously don't). You could power the flash down to 2.7V or 3.0V in which case VIHmin would be 1.62V and 1.8V respectively. 

 Jake

[Altera_Forum]

Ideally I'll power the FLASH from 1.8V as well.

[Altera_Forum]

1.8V VCCIO for MSEL[], and these pins can be connected with 3.3V, isn't it?!