I am excepting the following LUT to be inferred as RAM/ROM, so the synthesis time can be reduced (since the LUT below is quite large, and there are several other LUT's in the code). Are there any settings that will allow the following code to be recognized as RAM/ROM, or are there any ways the Verilog code can be modified?
Currently, Quartus is giving me the message, "uninferred due to asynchorous read logic".
always @(sin_table1_in) begin
case(sin_table1_in)
9'd0 : table1_out = 1449;
9'd1 : table1_out = 1451;
9'd2 : table1_out = 1453;
9'd3 : table1_out = 1455;
9'd4 : table1_out = 1457;
9'd5 : table1_out = 1460;
9'd6 : table1_out = 1462;
---
9'd510 : table1_out = 2047;
9'd511 : table1_out = 2047;
default: table1_out = 2047;
endcase
end
