ddr2 tco skew to high?

[Altera_Forum]

I generated a ddr2 controler with cyclone2 ip core. 

 when i full complation used quartus2 7.2, it warning TCO skew between clock to sdram pins too high at 135ps.   how to solve it? THANK YOU !

[Altera_Forum]

The simple answer is to manually place the clk output pins. They all need to be on the same type of pin, differential clock output pairs are a good choice

[Altera_Forum]

thank you,my clock already is differential clock,and the clock pin was generated by the IP core