Problem to generate the design with Synplify

[Altera_Forum]

Hello, 

 I encounter some issues in order to generate my Leon3 design.  I'm using Synplify v9.6.2 for the synthesis and Quartus II v8.1 for the place and route.  I obtain 708 errors during the place and route phase. The following is an extract of the errors list :  ... Error: WYSIWYG primitive "un8_cpt_clk_divided_9_" is not compatible with the current device family File: /projets/grlib/designs/test/synplify/leon3mp.edf Line: 619906 Error: WYSIWYG primitive "un8_cpt_clk_divided_8_" is not compatible with the current device family File: /projets/grlib/designs/test/synplify/leon3mp.edf Line: 619917 Error: WYSIWYG primitive "un8_cpt_clk_divided_7_" is not compatible with the current device family File: /projets/grlib/designs/test/synplify/leon3mp.edf Line: 619928 Error: WYSIWYG primitive "clklock_1_cZ" is not compatible with the current device family File: /projets/grlib/designs/test/synplify/leon3mp.edf Line: 619938 Error: WYSIWYG primitive "clk_divided_0_0_cZ" is not compatible with the current device family File: /projets/grlib/designs/test/synplify/leon3mp.edf Line: 619948 ...  I precise I can generate without errors the same design using Quartus II 8.1 for the synthesis and place & route phase. Moreover I confirm I have selected the same FPGA target (EP3C40) in Synplify and Quartus. Therefore I think there is a problem of compatibility between Synplify and Quartus.  As my flow design process recommends to use Synplify, I would like to know if you have a solution to resolve this problem.  Julien

[Altera_Forum]

--- Quote Start ---  Hello,  I encounter some issues in order to generate my Leon3 design.  I'm using Synplify v9.6.2 for the synthesis and Quartus II v8.1 for the place and route.  I obtain 708 errors during the place and route phase. The following is an extract of the errors list :  ... Error: WYSIWYG primitive "un8_cpt_clk_divided_9_" is not compatible with the current device family File: /projets/grlib/designs/test/synplify/leon3mp.edf Line: 619906 Error: WYSIWYG primitive "un8_cpt_clk_divided_8_" is not compatible with the current device family File: /projets/grlib/designs/test/synplify/leon3mp.edf Line: 619917 Error: WYSIWYG primitive "un8_cpt_clk_divided_7_" is not compatible with the current device family File: /projets/grlib/designs/test/synplify/leon3mp.edf Line: 619928 Error: WYSIWYG primitive "clklock_1_cZ" is not compatible with the current device family File: /projets/grlib/designs/test/synplify/leon3mp.edf Line: 619938 Error: WYSIWYG primitive "clk_divided_0_0_cZ" is not compatible with the current device family File: /projets/grlib/designs/test/synplify/leon3mp.edf Line: 619948 ...  I precise I can generate without errors the same design using Quartus II 8.1 for the synthesis and place & route phase. Moreover I confirm I have selected the same FPGA target (EP3C40) in Synplify and Quartus. Therefore I think there is a problem of compatibility between Synplify and Quartus.  As my flow design process recommends to use Synplify, I would like to know if you have a solution to resolve this problem.  Julien  --- Quote End ---    Hi,  first think I'm wondering is that you are using an EDIF netlist. The default for Atera devices at least in SynplifyPro is a vqm netlist. Unfortunately I have no access to Synplify.  Are you really sure that you choose the correct device ? The only way to force SynplifyPro to generate an EDIF netlist for Altera is to choose e.g MAX device .  Can you post your SynplifyPro .prj File ?  Kind regards  GPK