multiple clock domain instruction

[Altera_Forum]

Hi, guys, 

 I am now studying the document named "building systems with multiple clock domains" which is in Quartux II Handbook, Volume 4.  in page 11-8, it says that I need to find something inside the file standard.bdf, however, I spend hours finding the standard.bdf file but couldn't find it in my computer. I am pretty sure I did correctly in the previous steps...  Anybody knows where the file is? I am kinda rookie to the altera software for now..  thanks a lot

[Altera_Forum]

standard is the design name for which ever device you are targeting, and the bdf should be in that directory. did you check: 

 <Nios II EDS install path>\examples\<verilog or vhdl>\<board  version>\standard

[Altera_Forum]

hello 

 Maybe this thread is useful for you  http://www.alteraforum.com/forum/showthread.php?t=6627&highlight=dabg  Chao  DABG

[Altera_Forum]

--- Quote Start ---  standard is the design name for which ever device you are targeting, and the bdf should be in that directory. did you check:  <Nios II EDS install path>\examples\<verilog or vhdl>\<board  version>\standard  --- Quote End ---    thanks for the reply. Exactly, there is such a directory! I thought the bdf file might be there after I generated the updated system using SOPC builder; however, it is not there!! :confused:  where else can i check? thank you

[Altera_Forum]

--- Quote Start ---  hello  Maybe this thread is useful for you  http://www.alteraforum.com/forum/showthread.php?t=6627&highlight=dabg  Chao  DABG  --- Quote End ---     Hi, thanks for the link.. sorry that I didn't see the info abt bdf file there. Where could i find it or download it or need to generate or just draw it myself (quite impossible)?

[Altera_Forum]

--- Quote Start ---  standard is the design name for which ever device you are targeting, and the bdf should be in that directory. did you check:  <Nios II EDS install path>\examples\<verilog or vhdl>\<board  version>\standard  --- Quote End ---    and there is a bsf file only...

[Altera_Forum]

please help~~ =(

[Altera_Forum]

i don't see any bdf files either. the manual must be out dated. 

 you will have to create the bdf or work with the HDL file instead.

[Altera_Forum]

Hello, 

 I am not sure if I understood your question, but for manage multiple clock domain you can use a double clock fifo.  You can generate this fifo using the MEGAWIZARD PLUG IN MANAGER.  tools>>megawizard plug in manager>>create...>>memory_compiler>>fifo  Good luck.

[Altera_Forum]

thank you. maybe you are right, but the v code seems quite complicated

[Altera_Forum]

ok. let me try, thank you =)