Problem on JTAG and SignalTAP debugging

[Altera_Forum]

2 problems 

 1) JTAG is not stable, on STP there always showed invalid jtag connection or data transmitting error. sometimes the STP can work properly.  the line between jtag cable and fpga device is rather short. and I've tested the signal quality as well as powers of fpga. No problem found. The powers are rather good, only 10mV vpkpk noise.  2) I use STP to capture state machine's value, I found the state swithed to a value that I never defined. What's wrong with it?  Highly appreciated if anyone can give advice. thank you!

[Altera_Forum]

--- Quote Start ---  2 problems  1) JTAG is not stable, on STP there always showed invalid jtag connection or data transmitting error. sometimes the STP can work properly.  the line between jtag cable and fpga device is rather short. and I've tested the signal quality as well as powers of fpga. No problem found. The powers are rather good, only 10mV vpkpk noise.  2) I use STP to capture state machine's value, I found the state swithed to a value that I never defined. What's wrong with it?  Highly appreciated if anyone can give advice. thank you!  --- Quote End ---    Hi,  what kind of programming HW do you use ? No overshoots on your Jtag signals ?  Kind regards  GPK

[Altera_Forum]

Hi Guys, 

 I've sovled the problem last night. I added a 18pF capacitor to signal tck and ground. Then all OK.  It is strange that there's no waveform difference on oscilloscope between with and without the capacitor. And also JTAG is a low speed bus, which on my board only connect with one device. I guess there might be a weak point on jtag circuit/IO design of cyclone 3 fpga.  There used to be same problem on Xilinx spartan3, but now I used the Virtex4, no such a problem any more.

[Altera_Forum]

--- Quote Start ---  Hi Guys,  I've sovled the problem last night. I added a 18pF capacitor to signal tck and ground. Then all OK.  It is strange that there's no waveform difference on oscilloscope between with and without the capacitor. And also JTAG is a low speed bus, which on my board only connect with one device. I guess there might be a weak point on jtag circuit/IO design of cyclone 3 fpga.  There used to be same problem on Xilinx spartan3, but now I used the Virtex4, no such a problem any more.  --- Quote End ---    Hi,  maybe you have had very small overshoots at the edges of your Clock signal ??  Kind regards  GPK

[Altera_Forum]

I think, it's a signal quality problem though. Although JTAG is operated as a slow bus with TCK of 6 MHz, it's specified for 25 MHz operation. The involved FPGA hardware shouldn't be expected slower than other logic cells, so a short ringing in the TCK edge can easily cause false clocking. 

 Another popular candidate for JTAG failure is crosstalk from other fast signals on the board. Installing the said parallel capacitor slows down TCK edges but reduces also the crosstalk susceptibility.  Finally, some systems involving a high interference level, e.g. in the power electronics field, may effectively refuse usage of standard JTAG hardware during active operation. Special measures, e.g. optical isolated interfaces are required in this case.