rdreq didnt read all the data in dcFIFO (functional simulation)

[Altera_Forum]

hi,  

 i have question regarding to rdreq in DCFIFO. i'm writing 4 16-bits data into dcFIFO at 100Mhz speed. and read at 200Mhz speed. the problem now is, rdreq didnt read all 4 data in FIFO. only 3 available(data2,data3 and data4 only). data 1 is missing. i run for functional simulation only.   could someone help me on this? i'm stuck almost 1 day already.  DCFIFO setting and simulation output attached.   Thanks  -Farhan

[Altera_Forum]

can someone help me? :(

[Altera_Forum]

Note that at beginning wrfull pin is high, so, first write attempt is ignored.

[Altera_Forum]

wrfull looks high on that first write. There is circuitry on by default that disables extra writes/reads when full or empty, as that can completely corrupt the fifo.

[Altera_Forum]

ok.noted.  

 now, i have another issue when combining my sub blocks (datapath + CU).   when i simulated the datapath block separately, data is read out nicely in 4 clock cycles at every rising edge during rdreq is HIGH. but, now, when i tested in combined block with CU, it's failed. FYI, rdreq(read_fifo) is not controlled by CU. i control it manually. this CU is responsible for write operation(which is successful simulated). rdreq depends on "Routerclk" and writereq(write_fifo) depends on "clk".   i attached the simulation for combined design + FBD + successful simulation for Non combined design.   As u can see in the encapunitsimulation picture, the data is written to FIFO(during write_fifo is HIGH). FOUR 16-bit data is written to FIFO(i put the number in pink color). but, when rdreq is HIGH(read_fifo is HIGH), it's missed the last data, which is 0000000000000000. encapunitsimulation2 shows weird counting of the data in fifo.   i want the data to be read out as in simulationnoncombined picture.   (functional test simulation).  Please help.   Thanks Guru..

[Altera_Forum]

can someone help me on this? 

 Thanks a lot!