Is it possible to use Simplify for Nios2

Altera_Forum · ‎05-23-2005

I want to use Simplify for compilation process of my NIos2 system

Can someone explain how to do it ?

In my project i have one part in AHDL and all other files in Verilog

Top level is ALEXS_BOARD_BLOCK.dbf (is block diagramm)

I was trying to set extarnal compilation tool in quatrus

My steps is :

1. Open workable design

2. Open project settings

3. Open "EDA Tool Settings"->"Design Entry & Synthesis"

4. Select Tool name -> "Synplify Pro"

5. Set Format - 'Verilog HDL"

6. Set checkbox - "Run this tool automaticaly.... "

7. Select Library Mapping File "C:/Program Files/synplicity/Synplify_73/lib/synplcty.lmf" (it present)

8. Click OK

9. run synthesis

And have following srr file from simplify

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$ Start of Compile# Mon May 23 09:07:52 2005

Synplicity Verilog Compiler, version Compilers 7.3, Build 073R, built May 30 2003

Verilog syntax check successful!

@E|No component with name ALEXS_BOARD_BLOCK to synthesize

@END

Process took 0h:0m:0s realtime, 0h:0m:0s cputime

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How to fix this ?