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Hello,
The system includes a 32 bit Avalon-Slave which needs the byteenable for the correct function. A DMA is reading some data from the slave. Regardless of the defined DMA data width (ALTERA_AVALON_DMA_CONTROL_BYTE_MSK, ALTERA_AVALON_DMA_CONTROL_HW_MSK, ALTERA_AVALON_DMA_CONTROL_WORD_MSK) byteenable is always “1111” during a read cycle. The value of byteenable is correct when writing via DMA or when using IORD_8DIRECT, IORD_16DIRECT, IORD_32DIRECT. Is it possible to force the DMA to use the correct byteenable value? At page 50 of mnl_avalon_bus.pdf it is mentioned that a master read transfer does not use byteenable. I think that this is the answer of the above problem. But now I wonder why this was implemented in this way. Regards, niosIIuserLink Copied
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