no Nios II CPUs with debug modules available

[Altera_Forum]

I re-compiled the sof file of my project and having downloaded it whit Quartus II programmer, I got this error in Nios, when trying to debug the Nios software: 

 there are no nios ii cpus with debug modules available which match the values specified. please check that your pld is correctly configured, downloading a new sof file if necessary.  I tried downloading once again the .sof file, recompiling it, rebooting the pc, etc etc but I always obtain this same error.  Yesterday I retried, and everything worked fine!! But after another generation of the sof file, the problem was back... Today it never worked. I'm using quartus II 5.0 (didn't install the ALTSYNCRAM patch since it says I haven't installed 5.0 (?!)) and Nios 5.0.  Has anyone ever got this error? Thank you  Marco

[Altera_Forum]

Here are some things to check: 

 1) Use the system ID peripheral and make sure the Nios II IDE checks it 2) Make sure you have the correct download cable selected 3) Make sure you have met timing in Quartus II 4) If you are using a Nios development board make sure unused I/O are set to tri-state (this is the usual setting for most boards but make sure you know what you are doing before making this setting change) 5) Make sure you have assigned your I/O to where you expect (if you let Quartus II auto assign I/O it will put the I/O wherever it makes sense in terms of timing)

[Altera_Forum]

--- Quote Start ---  originally posted by badomen@Jun 17 2005, 11:37 AM 5)  make sure you have assigned your i/o to where you expect (if you let quartus ii auto assign i/o it will put the i/o wherever it makes sense in terms of timing)  --- Quote End ---   I am having similar issues, and in the info that Quartus II spits out it says "No exact pin location assignment(s) for 4 pins of 180 total pins." the pins are  altera_reserved_tdo altera_reserved_tms altera_reserved_tck altera_reserved_tdi  Do i have to assign these to specific pins? I'm using the Nios II Cyclone dev board.  -jon

[Altera_Forum]

Those ones are automatically assigned by Quartus (that's why you don't put them in your design). 

 What I meant by auto assign is lets say you have a PIO with 8 output bits. You then connect an 8 bit set of I/O to it but you don&#39;t use Quartus or the SOPC Builder pin mapper to assign them. Quartus will look at those I/O and route them in such a way to get the best timing possible (so if the PIO registers are on the left side of the FPGA it won&#39;t wire those to the right side I/O if it can help it). Now sometimes people run into problems when they let Quartus do this automatically because it may route these signals to devices on your board then cause all kinds of problems.  Here&#39;s an example (Nios development board): You let Quartus auto-assign a PIO pin and it chooses to pick the PLD-reconfig pin ...... the first time you write to the PIO you may trigger a reconfiguration condition. The reason why I choose that example is that it ties into my other point: <div class='quotetop'>QUOTE </div>  --- Quote Start ---  4) If you are using a Nios development board make sure unused I/O are set to tri-state[/b]  --- Quote End ---    If you download to a Nios dev. board and the project is not set to tri-state unused I/O (set to ground by default) then after programing the design will trigger a reset (which will cause your design with an OCI core to disappear under some cases). This is a pretty interesting case when your design is programmed from flash because you enter this loop:  1) Board powers up 2) Max part programs the FPGA with the image out of Flash 3) FPGA design triggers a re-config 4) Go back to step 2  (your board gets stuck in a programming loop, you&#39;ll notice the LEDs flashing on and off a lot).  This probably doesn&#39;t help motumboe but since we were on the topic I wanted to share that to save someone else some headaches.

[Altera_Forum]

Hi have had the same problem, after a lot of time i found the cause on Jtag signal, i solved with appropiate resistor and 100pF from jtag clock and ground.  

See my topic 2/3 page back on this forum.  roberto

[Altera_Forum]

Thank you all for your replies :-) 

I&#39;m trying the suggested solutions and I&#39;ll let you know whether I solve the problem! Regards,  Marco