Nios® V/II Embedded Design Suite (EDS)
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I got "Verify failed "again.

Altera_Forum
Honored Contributor II
‎06-21-2005 08:34 AM
938 Views

I'm using UP3 development kit. I'm doing Designing a NiosII system from Scratch for UP3 and following the instruction tutorial. 

 

I have done adding CPU&Peripherals:  

* NiosII 32-bits CUP 

*JTAG UART 

*Timer 

*Avalon Tri State Bridge 

*SLS_UP3_SRAM 

*LED_PIO. 

 

Every element is same the tutorial. But I can't get write back from memory. I always get "Verify failed". I have no any idea for this. The problem like blow: 

 

sing cable "ByteBlasterII [LPT1]", device 1, instance 0x00 

Processor is already paused 

 

Downloading 00000000 ( 0%) 

Downloaded 53KB in 0.0s  

 

Verifying 00000000 ( 0%) 

Verify failed  

Leaving target processor paused
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