Hi,
The Performance Counter module in my Nios II system (v1.1) does not work (timing and counting registers are stuck to 0). I tried to isolate the problem on a simple Nios II system and found out that this behaviour only occurs if the Nios II system is implemented in VHDL. The same implementation in Verilog is ok.
It seems to me that something goes wrong during synthesis because Quartus II (v4.2, SP 1 installed) produces a lot of warnings (e.g. "Warning: Tied undriven net "performance_counter_control_slave_address[4]" at NIOS.vhd(2435) to GND or VCC") indicating that signals belonging to the performance counter module are stuck to VCC or GND.
Does anybody know what's wrong with the VHDL version of the performance counter in my design and how to fix the problem?
Thanks!
jackie
