Hi gregoryw,
Avalon read and write signals can be derived from wb cyc, stb, and we.
Use the (cyc & stb) to qualify the cycle and we to drive either read or write.
Unless your wb master is the only master for a particular slave, you'll need
to add some logic to handle the ACK -- which is basically the opposite of the
avalon ready ... since you'll have to wait for the avalon arbiter to grant your
master access.
Avalon slaves don't generate retries ... so you can just negate the RTY signal.
You should carefully review the Wishbone Bus Specification though. It's all there
and you'll save yourself lots of headaches if you spend a few hours reading it ;-)
Regards,
--Scott
