Custom Component with Master & Slave ports

Altera_Forum · ‎07-08-2005

I'd like to edit a custom component to have both master and slave ports tie to the Avalon Switch Fabric such that it can receive bus transfers from NIOS II and/or initiate bus transfers to access an on-chip RAM built in SOPC Builder.

The slave ports have been tied to the ASF with no problems using:

clock (input)

reset (input)

chip select (input)

write strobe (input)

read strobe (input)

write data bus (input)

read data bus (output)

address bus (input)

interrupt (output)

In the component editor, for it to be a master, these are the signals that seem to be needed:

clk (input)

waitrequest or interrupt (input)

write strobe (output)

read strobe (output)

write data bus (output)

read data bus (input)

address bus (output)

1) From reading about the wait request line, whenever other masters (NIOS II or DMA) are initiating, this line will tell other masters to not initiate any transactions. Say the NIOS II writes an instruction to my custom logic to grab the data from the on-chip memory and send it off-board, would this line be active such that it will prevent my custom logic from functioning?

2) I am only going to access a specific on-chip memory with address range of, say, 0x904000-0x904FFF, what Avalon Switch Fabric signals are needed from the custom logic to read and write to that memory space?

Altera_Forum · ‎07-25-2005

You can make it as show here:

CLASS user_logic_Camelot_Ethernet_Monitor
{
   ASSOCIATED_FILES 
   {
      Add_Program = "";
      Edit_Program = "";
      Generator_Program = "mk_user_logic_Camelot_Ethernet_Monitor.pl";
   }
   MODULE_DEFAULTS 
   {
      class = "user_logic_Camelot_Ethernet_Monitor";
      class_version = "2.0";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Date_Modified = "--unknown--";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
      PORT_WIRING 
      {
      }
      MASTER monitor_avalon_master
  {
            SYSTEM_BUILDER_INFO
     {
    Bus_Type = "avalon";
    Address_Width = "32";
  Max_Address_Width = "32";
  Data_Width = "32";
  Is_Enabled = "1";
          }
            PORT_WIRING
     {  
              PORT clk
              {
               width = "1";
               direction = "input";
               type = "clk";
              }
              PORT reset
              {
               width = "1";
               direction = "input";
               type = "reset";
              }
              PORT address
              {
               width = "32";
               direction = "output";
               type = "address";
              }
              PORT byteenable
              {
               width = "4";
               direction = "output";
               type = "byteenable";
              }
              PORT read
              {
               width = "1";
               direction = "output";
               type = "read";
              }
              PORT readdata
              {
               width = "32";
               direction = "input";
               type = "readdata";
              }
              PORT write
              {
               width = "1";
               direction = "output";
               type = "write";
              }
              PORT writedata
              {
               width = "32";
               direction = "output";
               type = "writedata";
              }
              PORT waitrequest
              {
               width = "1";
               direction = "input";
               type = "waitrequest";
              }
            }
         }
      SLAVE monitor_avalon_slave
  {  
     SYSTEM_BUILDER_INFO
     {
  Bus_Type = "avalon";
                Address_Alignment = "native";
                Address_Width = "2";
                Data_Width = "32";
                Has_IRQ = "1";
                Has_Base_Address = "1";
                Read_Wait_States = "0";
                Write_Wait_States = "0";
                Setup_Time = "0";
                Hold_Time = "0";
                Is_Memory_Device = "0";
                Uses_Tri_State_Data_Bus = "0";
                Is_Enabled = "1";
     }
     PORT_WIRING
     {
              PORT chipselect
              {
               width = "1";
               direction = "input";
               type = "chipselect";
              }
              PORT saddress
              {
               width = "2";
               direction = "input";
               type = "address";
              }
              PORT irq
              {
               width = "1";
               direction = "output";
               type = "irq";
              }
              PORT swrite
              {
               width = "1";
               direction = "input";
               type = "write";
              }
              PORT swritedata
              {
               width = "32";
               direction = "input";
               type = "writedata";
              }
           }
         }
   }
   USER_INTERFACE 
   {
      USER_LABELS 
      {
         name = "Camelot_Ethernet_Monitor";
         technology = "Camelot";
      }
   }
   DEFAULT_GENERATOR 
   {
      top_module_name = "monitor";
      black_box = "0";
      vhdl_synthesis_files = "";
      verilog_synthesis_files = "monitor.v";
      black_box_files = "";
   }
}