On chip ram efficiency

[Altera_Forum]

Hi all, 

 Can anyone say to me how many clock cycles needs an onchip ram from a stratix device for reading a word from it? I thought that it just took one cycle, but seeing the docs it seems to be 2 cycles.  And another question:  How can I use an onchip ram with double port in my nios2 design? I'm trying to use a double port onchip ram and connect one port to the instrucion bus and the other port to the data bus, but I'm not being able to link the program with the autogenerated linker script. I have written a linker script, but I don't know where to place it, because when I try to tell the nios2 ide to use my linker script nothing appears in the browse window. Wich extension must be the linker script file, ldi, lkr, lnk ...?  Can anyone help me?  Thanks.  Best regards,  PeiBoL

[Altera_Forum]

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  I have written a linker script, but I don&#39;t know where to place it, because when I try to tell the nios2 ide to use my linker script nothing appears in the browse window. Wich extension must be the linker script file, ldi, lkr, lnk ...?[/b]  --- Quote End ---    The automatically generated script is in <syslib>/[Debug|Release]/system_description/generated.x, so placing your custom linker script in that directory will work. Actually, I think all you have to do is place it anywhere in your <syslib> directory.  Regarding your other questions, I&#39;m not sure.  - slacker

[Altera_Forum]

The on-chip RAMs in Stratix and Cyclone devices can be configured to have a 1 cycle read or a 2 cycle read. 

The 2 cycle read potentially offers higher frequency operation because the read data is registered. The inputs (address and write data) are always registered.