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Does anyone know the PHY address (0 - 31) for the Nios II Evaluation board? I can't find a schematic from Altera for the evaluation board and there is not much documentation out for the board.
Thanks, JonLink Copied
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Hi Jon,
I believe there was one schematic file omitted with the first Nios II release with the 1C12 eval board... in Nios II 5.0 this doc was added back in. In my installation I see it as "nios2_evaluation"1c12_board_schematic.pdf". On page 6 of this document is what appears to be the ethernet PHY. All phyad pins (phyad[4..0]) are tied to ground on this schematic. Hope this helps!- Mark as New
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Jesse,
Thanks! exactly what i was looking for. I should remember to search my maching first next time...
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