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Hello:
Now I want to make a sdram daughtercard.But in my board the PLL external clk out pins have all been used,so I have to use the internal PLL output clock signal to drive the sdram.I want to ask if the internal clock signal is stable to drive the sdram?whar problems should I care for?Link Copied
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Hi jigdo,
> I want to ask if the internal clock signal is stable to drive the sdram? Depending on your design, you may have some jitter issues. However, I use a compensated output to drive my SDRAM clock via an I/O pin on one of my boards without any problems -- although the clock is only 50 MHz. > whar problems should I care for? You will have to consider any routing delay that will affect the phase relationship WRT your system clock and adjust as necessary in your PLL configuration. Regards, --Scott- Mark as New
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Hi smcnutt:
Thank you! I will try .
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