Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
12585 Discussions

IORD_XDIRECT AND IOWR_XDIRECT?

Altera_Forum
Honored Contributor II
1,064 Views

Hello: 

 

Now I have some problems about the I/O Marco IORD_XDIRECT AND IOWR_XDIRECT.For example: 

I have a 16 bits slave periphery and the BEn0 ,BEn1 are both always low(means that the upper 8 bits and the lower 8 bits are both used).Make sure the front point no problem,now I use the sentense IOWR_8DIRECT (base,odd_addr,data8),the result I think is that the upper 8 bits is the data8,the lower 8 bits 

is xxxxxxxx.If using even address,the result is opposit.But I am not sure it is right or wrong?
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
245 Views

I look up "io.h" which define the "IORD/IOWR", and then "stb / stbio, lbu/lbuio....." in the Instruction Set Reference of NIOSII. I can't understand the specification about those instructions. 

 

Can someone help us to explain what they work out detailly?
0 Kudos
Altera_Forum
Honored Contributor II
245 Views

Look at Table 3.5 of the Processor Reference Handbook 

 

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  

ldbio 

ldbuio 

stbio 

ldhio 

ldhuio 

sthio 

These operations load/store byte and half-word data from/to peripherals without caching or 

buffering.[/b] 

--- Quote End ---  

0 Kudos
Altera_Forum
Honored Contributor II
245 Views

Hi mountain8848, 

 

The stb and stbio are used to store a byte (from memory). The stbio instruction 

bypasses the data cache, the stb does not. 

 

 

The ldbu and ldbuio are used to load a byte (from memory). The lduio instruction 

bypassess the data cache, the ldbu does not. The "u" just means that the 

high-order bits in the target register are set to zero (unsigned) rather than 

being sign-extended. 

 

Regards, 

--Scott
0 Kudos
Reply