Using SDRAM Controller on Development Board

[Altera_Forum]

Hi, 

 Does anyone have experience sharing the 32 MBytes of SDRAM that is installed on the DSP Development Kit board between the Nios II and some custom FPGA circuitry?  I would like to dedicate some portion SDRAM (e.g. 8 MBytes) that is installed on the Stratix II DSP Development Kit and use the the SDRAM controller with the Avalon Interface that is provided as part of the Nios II development kit CD. The remaining portion portion of the SDRAM (e.g. 24 MBytes) would be used to store samples acquired from the on-board A/D. The custom FPGA circuitry would only store the 8 MSb's of each 12-bit A/D sample and then accumulate eight samples in an internal FIFO before writing the data out to the SDRAM as a 64-bit word. This would then reduce the rate of the SDRAM writes to 1/8 of the A/D sample rate. I would like to store 8-bit A/D @ 100 MHz so this would translate to providing 64-bit data to the SDRAM's @ 12.5 MHz.  Can the Avalon switching network sustain a 12.5 MHz @ 64-bits/sample rate when writing data to a shared SDRAM resource between the Nios II and custom FPGA circuitry while allowing the Nios II to run it's OS/application out of SDRAM simultaneously?  Any information would be appreciated.  Brad S.

[Altera_Forum]

Use a DMA to handle the transfer from converter to memory. 

Then you have a shared resource with two masters, processor and DMA. You can setup priority on each to ensure bandwidth. 12.5 MHZ on a 50MHz system gives a load of 25 - 35 % including overhead, that looks OK if hte processore does not use nore than the rest.

[Altera_Forum]

--- Quote Start ---  originally posted by jhansen@Jul 22 2005, 03:42 AM use a dma to handle the transfer from converter to memory. then you have a shared resource with two masters, processor and dma. you can setup priority on each to ensure bandwidth. 12.5 mhz on a 50mhz system gives a load of 25 - 35 % including overhead, that looks ok if hte processore does not use nore than the rest.  --- Quote End ---    Would the DMA transfers between the A/D and SDRAM be handled by the Nios II core or would a separate DMA controller generated using SOPC act as the 2nd master with the SDRAM providing slave-side arbitration between the Nios II and DMA controller?  Also, how difficult is it to create custom FPGA circuitry that interface to the avalon-based DMA controller that transfer data from a the A/D-samples FIFO @ 12.5 MHz and store it on the SDRAM within a specified address range? Effectively you would have the DMA controller master facilitating the transfer between two slave devices (A/D & SDRAM).  Brad.