Avalon_bus_to_extenal_controller

[Altera_Forum]

As i am a newbie with sopc, i do not understand very well how to interface Altera peripheral (Avalon slave interface) with an external 16 bits microcontroller (the real master). I do not want to implement any nios inside the fpga.  

 Do i have to create an 'inteface to user logic' with an Avalon master on one side (fpga), and an external 16 bus on the other side (microncontroller). How to generate the Avalon timing from the 16 bits bus timing? Is there somewhere an example?

[Altera_Forum]

I am puzzled. Why not "I do not want to implement any nios inside the fpga." but using "Avalon slave interface"? I don't know using a bus-on-chip without a CPU-on-chip to access the bus.

[Altera_Forum]

Well, the on board cpu is a 16 bit microcontroller. The idea is to make a bridge wich will transform the external cpu timing to an avalon compatible timing.  

Into the fpga will be only avalon slave functions (uart, dp_ram, state sequencer...). Our application do not need a 32 bit processor, but a deterministic timing. The FPGA will act as a peripheral (i.e. co-processing).  Do somebody have made a similar bus (i only found large buses as AHB, EMIF) bridge?  Best regards.  Jacques Paris

[Altera_Forum]

Although you know your product better than anyone here, wouldn't it be more cost effective to use a Nios instead of an external 16 bit microcontroller taking up board space and extra cost? You may find the 'e' core does what you need and small enough to justify the change. 

 Anyway ...... your first post is pretty much what you would want to do. Your external signals will need some sort of glue logic to adapt them over to Avalon master signals then all your peripherals in SOPC builder connect to the Avalon master interface. So the real work is making sure you create a bridge that obeys the Avalon spec.

[Altera_Forum]

As my product need one microcontroller and several state machines, i have to write such a bridge. I will try to make it with "Interface to custom logic" in the sopc builder. 

It is not evident for me which signals (ce,wr,rd, adr 0-15, datd 0-15, clk) do an avalon master need from outside. Do somebody has an example for a bus interface?

[Altera_Forum]

i have a similar problem ,i want generate a double accessed ram in FPGA,with one side communicating with niosII cpu and the other side communicating with dsp out of FPGA,but i dont know how to make it. you know,each side of the double accessed ram is slave port,when i generate it in sopc buider,the two sides all connect with niosII cpu. i have no idea about it. do you have solved your problem, if you do,maybe you will give me some idea.