Creating SOPC-aware DMA slave device

Altera_Forum · ‎07-23-2005

Hi,

I would like to use use the DMA controller found within SOPC to transfer data between a FIFO that will be connected as the DMA read master and the SDRAM controller that will be connected to the write master port. The FIFO will be based from custom FPGA circuitry and will acquire data samples from both of the A/D's (@ 100 MSamples/sec) that are installed on the DSP Development kit board and use a FIFO to produce a 64-bit wide data path @ 12.5 MHz.

How do I create a custom device (FIFO) that will be can be selected from within SOPC? Once seen by SOPC, I should be able to connect the FIFO to the read master port of the DMA controller and the write master port would be connected to the SDRAM controller to perform the required transfers without dropping any samples or interrupting any normal Nios II processing on its dedicated portion of the SDRAM.

Has anyone created a custom SOPC-aware device that can be connected to the DMA controller to either the read or write master ports? Is there some documentation on how to creating custom SOPC-aware components?

Any comments would be helpful and appreciated.

Sincerely,

Brad.

Altera_Forum · ‎07-25-2005

Hello Brad,

I have created a custom SOPC component that makes use of the DMA as a READ and WRITE MASTER, with the component just a read slave. The READ portion of the DMA is conected to memory, SRAM in my case, and the WRITE portion is connected to my logic.

I used the streaming mode of transfer for packets and a MEGA WIZARD for my fifo. I have a little logic that helps pace the incoming data to the WRITE portion of the FIFO.

It works fine.

-Baycool

Altera_Forum · ‎07-26-2005

Hi Baycool,

Sounds like you have made an SOPC component that is very similar to the type we will be needing. To the best of your knowledge, is there any documentation on how to create a custom SOPC component or did you just use the documentation that is referenced from within the SOPC application itself?

Our FIFO will probably have to be made from custom VHDL code but that's probably the easy part. So far, the potential stumbling block has been finding a way to create a custom SOPC component that uses the FIFO and DMA controller to make an efficient A/D to SDRAM transfer mechanism.

Thanks for the info.

Brad.

Altera_Forum · ‎07-26-2005

Hi Brad,

I think there are some app notes from www.altera.com. Also, if you reference the Avalon Bus Specification that will help.(AN-333 Developing Peripherals for SOPC Builder)

Creating a custom SOPC component is easy if you use the wizard in SOPC builder. Just build the interface as you would any interface. Then whether you are using VHDL or Verilog, the wizard will help you match port names for an Avalon component to your component. Any port name that does not match up is defined as an EXPORT type of signal.

The FIFO is easy to hook up if you use streaming data. The signals READYFORDATA and ENDOFPACKET are all that are needed (in addtion to normal slave signals) to implement a streaming transfer.

Make the FIFO signals qualify READYFORDATA,

Example( In Verilog):

assign readyfordata = ((fifo_cnt < 10'd1000) && (pixel_count < (800*600)) && (!sync_end_of_picture)) ? 1'b1 : 1'b0;

Where fifo_cnt is straight from the FIFO_DC component.

A few more tips:

1) I found when using the DMA to stream data you need to minimize the WRITE latency for your component. I can't remember off hand what the value is , either 1 or 0 waits.

2)Also, use the Nios sim ( AN-351), it was INVALUABLE in debugging a real DMA transfer. If you take this approach, you may want to preload data in your SDRAM for simulation, otherwise a simualtion will take forever. I wrote a nice little perl script that is referenced somewhere in the forum that will help.

3) Use the HAL paradigm to program the DMA. It is clean and works fine for Nios 5.0 and Quartus 5.0.

Hope this info is helpful.

-Baycool