Sequential Logic in Altera

[Altera_Forum]

Hi, 

  How to write a sequential logic in Altera(Verilog)? How to make use of clock & reset (say in a D flipflop)?  Could any one give me one example along with C program.

[Altera_Forum]

Hi Mohana, 

 > How to make use of clock & reset (say in a D flipflop)?  Read the avalon bus specification:  http://www.altera.com/literature/manual/mn...avalon_spec.pdf (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf)  > Could any one give me one example along with C program.  Take a look at the example (Nios-II) verilog designs -- a good starting point is the led_pio.v. It's a very basic output-only pio.  Regards, --Scott

[Altera_Forum]

i just looked at the led_pio.vhd (vhdl version) and can anyone enlighten me as to what std_logic' and std_logic_vector' do? Is that just a different way to type cast?  

 Thanks, Jon

[Altera_Forum]

I recommend you create a Verilog (.v file) or VHDL (.vhd) file in Quartus, then go to the edit menu and select "insert template". This will give you a bunch of different HDL (Hardware descriptive language) structured examples (including registers). 

 I also remember a HDL editor out there coming with a pretty good tutorial program for both VHDL and Verilog (these are the two main HDL language by the way)..... I forget what the name was but the editor did HDL entry and functional similuations. Maybe someone out there knows which one I'm talking about and can give jonb and mohana the name of it or some other good tutorial (google searching will find thousands of tutorials btw).

[Altera_Forum]

BadOmen, 

 I think you are thinking about ActiveHDL which does indeed come with a good set of tutorials for VHDL and Verilog. I guess I need to restate my question about the Altera code.   In the architecture of an LED they have the line clk_en <= std_logic&#39;(&#39;1&#39;); and in the process block they have another statement with std_logic_vector&#39;("0000000000000000000000000000000"). I understand what std_logic and std_logic_vector logic types are and I am assuming that is just a typecast since the clk_en is declared as std_logic, but I&#39;m just double checking.  thanks,  jon