ISR execution

[Altera_Forum]

Hello, 

 In chapter 6 of the Nios software development handbook, the section "ISR Performance" states:   <div class='quotetop'>QUOTE </div>  --- Quote Start ---  In the interests of performance, ISRs are normally executed with interrupts disabled. This action reduces the system overhead associated with interrupt processing, and simplifies ISR development, because the ISR does not need to be reentrant.[/b]  --- Quote End ---    What can I infer from this statement ? That when NIOS enters an ISR all interrupts are automatically disabled ? So, by default, there are no nested interrupts in NIOS ? And the functions alt_irq_interruptible() and alt_irq_non_interruptible() can be used to allow interrupts inside ISRs ?  Thanks  http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif

[Altera_Forum]

Hi eliben 

 Interrupts are automatically disabled means that the IE bit in the status register is cleared before executing the first instruction placed on the exception address. At the time the "eret" instruction is issued, the interrupts come back on, because the estatus register is copied to the status register.  If interrupts are enabled again or not, depends on the code executed from the exception address.   I think the default provided Altera interrupt handler is not reenabling interrupts. But you can write your own if you want.  Stefaan