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hi guys, im new here, so if i make any mistakes, please tell me
i have only been working with FPGA's and the Nios II for a week now, at my internship, but i have stumbled onto a rather big problem. we have been asked to devellop ethernet communication between a PC and a Cyclone on a certain board, which is equiped with a smsc lan 91c111 ethernet PHY. now the problem is that the board designers only made a 16 bit path to the ethernet phy, which isnt a problem for the ethernet phy, but the Nios II SOPC block for using the 91c111 demands a 32 bit data path to the chip, which we dont have a redesign of the board is not an option, especially since there are not enough free pins on the Cyclone to use a 32 bit path to the ethernet PHY so far, the only option i see is to build my own interface between the avalon bus and the ethernet chip, but with a 16 bit buss, but this most likely will take a lot of time, which i would like to spend on other things ( i only have about 15 more weeks here, and i would like to actually get some real work on the ethernet connection done, rather then getting the nios to even see the PHY) so my question is, do you guys have any smart ideas which might help out? any reference designs for a 16 bit interface which i missed? thanks for any repliesLink Copied
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This chip can operate with 8,16,or 32bit bus. For the lan91c111 component, select the ethernet daughtercard option which used a 16bit bus. When I did this before, I had to modify the component drivers to get it working on my custom board. Things may be easier under 5.0.
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