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Booting from EPCS4

Altera_Forum
Honored Contributor II
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Hi, 

 

We are developing the software for a custom board we designed and manufactured, so it's time for "burning" the software into the EPCS. We haven't included any CFI flash device in the design, only an EPCS4 for storing the FPGA configuration (EP1C12) and a program that should run at start-up. 

 

I tried to follow the steps described in the flash programmer user guide but it doesn't work, always get a "nios2-flash-programmer: Verification failure after write" message. 

 

 

What am I missing with this? How should I do for placing the software into the EPCS? 

 

 

The steps I followed were: 

 

1-Using the mk_target_board script, created the target board template. 

2-Opened the quartus project and generated the system with SOPCBuilder. 

3-Added the required pins (and assigments) for disabling all the other devices (external chips) in the real board. 

4-Compiled the design. 

 

Then with the real board design: 

5-Assigned the target board for the system, recopiled the design (NIOS-II and FPGA); 

6-Created and tested (debug mode on sdram) a small test application (makes a led blink). 

7-Compiled the test application (and system library) in release. 

 

And now with the flash programmer: 

8-Created a new flash programmer configuration, specifying the test application as the project (with the "program project into flash checkbox checked") and selecting the device configuration .sof file for the real hardware in the hardware image region of flash (EPCS)$; 

 

When tried to program the EPCS4, the results were these: 

 

Info: ******************************************************************* 

Info: Running Quartus II Convert_programming_file 

Info: Command: quartus_cpf --no_banner --convert --device=EPCS16 --option=standa 

rd.opt C:/projects/CustomBRD/NIOS2CPU/standard.sof standard.pof 

Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings 

Info: Processing ended: Sun Oct 02 02:03:10 2005 

Info: Elapsed time: 00:00:02 

Info: ******************************************************************* 

Info: Running Quartus II Convert_programming_file 

Info: Command: quartus_cpf --no_banner --convert standard.pof standard.rpd 

Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings 

Info: Processing ended: Sun Oct 02 02:03:11 2005 

Info: Elapsed time: 00:00:01 

# Programming flash with the FPGA configuration 

$SOPC_KIT_NIOS2/bin/nios2-flash-programmer --input=standard.flash --sof=c:/proye 

ctos/CustomBRD/nios2cpu/CustomBRDTemp/system/CustomBRDTemp.sof --epcs 

02-oct-2005 2:03:12 - (INFO) nios2-flash-programmer: Launching Quartus Programme 

r to download: 

c:/projects/CustomBRD/nios2cpu/CustomBRDTemp/system/CustomBRDTemp.sof 

Pre-Reading 163KBytes of data from U2: 

|----.----+----.----| 

********************* (3.063 sec). 

Erasing 3 Sectors: 

|----.----+----.----| 

********************* (2.937 sec). 

Writing 192KBytes : 

|----.----+----.----| 

********************* (3.078 sec). 

Verifying 192KBytes of data: 

|----.----+----.----| 

*******02-oct-2005 2:03:28 - (GRAVE) nios2-flash-programmer: Verification fa 

ilure after write. 

# Creating .flash file for the project 

$SOPC_KIT_NIOS2/bin/elf2flash --flash=U2 --epcs --base=0x0 --end=0x7fffffff --in 

put=MINITERM.elf --output=epcs_controller.flash --boot=$SOPC_KIT_NIO 

S2/components/altera_nios2/boot_loader_epcs.srec 

# Programming flash with the project 

$SOPC_KIT_NIOS2/bin/nios2-flash-programmer --input=epcs_controller.flash --sof=_ 

_NO_SOF_PLEASE__ --epcs 

02-oct-2005 2:03:29 - (INFO) nios2-flash-programmer: SOF-download skipped. 

Pre-Reading 24KBytes of data from U2: 

|----.----+----.----| 

********************* (0.828 sec). 

Writing 64KBytes : 

|----.----+----.----| 

********************* (1.031 sec). 

Verifying 64KBytes of data: 

|----.----+----.----| 

*********************02-oct-2005 2:03:34 - (GRAVE) nios2-flash-programmer: V 

erification failure after write. 

 

Thanks,
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3 Replies
Altera_Forum
Honored Contributor II
305 Views

Hi VLorenzo, 

 

> We haven't included any CFI flash device in the design, only an EPCS4 for 

> storing the FPGA configuration (EP1C12) and a program that should run  

> at start-up. 

 

Maybe, you should add cfi flash device to your flash programmer design, though you have no cfi flash in you project. You can refer to  

http://www.altera.com.cn/support/ip/processors/nios2/ips-nios2_devkit1.1-er.html#ideflash 

In Flash programmer failures on custom boards parts, 

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  

The flash programmer may fail if the custom target board does not contain a CFI flash component. Even if the board contains only an EPCS configuration device and no CFI flash, the target board system must contain a CFI flash component. 

 

Workaround: Add a CFI flash component to your target board in SOPC Builder.  You do not need to connect the flash signals to pins at the top level--you can leave them unconnected.[/b] 

--- Quote End ---  

 

 

I hope this can help you. 

 

LiangYi
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Altera_Forum
Honored Contributor II
305 Views

VLorenzo, 

 

I also use an EPCS4 to boot both FPGA configuration and firmware. I do not have any CFI component included in SOPC builder neither in the design nor in the custom board (Quartus 5.0.1) . With &#39;nios-flash-programmer&#39; I had similar effects. 

 

In another topic from 26th May 2005 (.... other topic) (http://www.niosforum.com/forum/index.php?showtopic=1752&hl=download+verification) wombat gave a hint in Post# 19 to suppress verification. I use this parameter wihout any problem. 

 

Mike
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Altera_Forum
Honored Contributor II
305 Views

Hi, 

 

It&#39;s solved. 

 

There was a bug in the epcs bootleader so needed to apply and do some other minor corrections as described in http://www.altera.com/support/ip/processor...vkit1.1-er.html (http://www.altera.com/support/ip/processors/nios2/ips-nios2_devkit1.1-er.html). 

 

Thanks to all
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