NIOS-II Cyclone II devboard timer problem

[Altera_Forum]

Hi all, 

my problem is with Cyclone II running NIOS-II. After creating a timer in SOPC builder and implementing it to my design, I am trying to generate periodic interrupts with some desired period. However, I can never create an interrupt with frequency higher than about 130kHz - e.g. I want to create 2MHz clock on some output pin, but this is not possible, since the interrupt won't occur, although the timer's timeout period should be set to minimal value (base frequency is 85MHz, so 1-clock period of the timer should be around 11.76ns):   IOWR_ALTERA_AVALON_TIMER_PERIODL(TMR2_BASE, 10); IOWR_ALTERA_AVALON_TIMER_PERIODH(TMR2_BASE, 0);  IOWR_ALTERA_AVALON_TIMER_CONTROL(TMR2_BASE, START_TIMER_WITH_IRQ_ONCE);  ---I am using uC/OS-II operating system, but I am not sure, if it can cause this problem.  Has anybody encountered similar problem? Any help is appreciated...

[Altera_Forum]

Good grief. 

 The problem is that your CPU simply lacks the time to handle all those spamming interrupts. It needs time to save state, handle the interrupt, and restore state.  For reference, a typical system tick clock runs at 100-1000 Hz; running faster than that tends to increase a scheduler's overhead by a great deal.  So, just what exactly are you trying to do? Generate a clock out? Pause execution for short periods?

[Altera_Forum]

--- Quote Start ---  originally posted by mike desimone@Oct 26 2005, 02:19 PM good grief.  the problem is that your cpu simply lacks the time to handle all those spamming interrupts.  it needs time to save state, handle the interrupt, and restore state.  for reference, a typical system tick clock runs at 100-1000 hz; running faster than that tends to increase a scheduler&#39;s overhead by a great deal.  so, just what exactly are you trying to do?  generate a clock out?  pause execution for short periods? <div align='right'><{post_snapback}> (index.php?act=findpost&pid=10612)  --- quote end ---    --- Quote End ---    Yes, I am trying to generate a clock signal for an external AD converter, frequency of 1-2MHz would be fine. Since I am quite new to RT-OS field and this is my first project with it, I lack some more insight.  I am still counting with the system clock frequency of 85MHz and try to derive and calculate the timing based on it, I think I should take more influence of OS into consideration - anyway I expected the rescheduling and context save/load faster and not to delay my application so much.  What would you suggest to me to create such a signal, either by software or hardware, so higher frequency can be reached?

[Altera_Forum]

--- Quote Start ---  originally posted by cableguy@Oct 27 2005, 03:54 AM what would you suggest to me to create such a signal, either by software or hardware, so higher frequency can be reached? <div align='right'><{post_snapback}> (index.php?act=findpost&pid=10623)  --- quote end ---    --- Quote End ---   Hardware, definitely.  If you want a free-running, steady clock signal, you just need a peripheral to generate it. Try this Verilog:  module ClockGenerator (    input clock,    input reset,    input chipselect,    input write,    input writedata,    output reg clockout ); reg count, limit; always @(posedge clock, posedge reset)    if(reset) begin        count <= 0;        limit<= 0;        clockout <= 0;    end    else begin        if(limit == 0)            clockout <= 0;        else if(count == limit) begin            count <= 0;            clockout <= ~clockout;        end        else            count <= count + 1;        if(chipselect && write)            limit<= writedata;    end endmodule  Take that, use SOPC Builder to make it into a component (set the pin types to the same as their names, except "clockout" should be "export" type), and add it to your system. Let&#39;s say you name it "clock_gen". When you generate the system, you&#39;ll have a clockout_from_the_clock_gen (or clockout_to_the_clock_gen? I can never remember) pin that you hook up to your ADC&#39;s clock.  In software, you just have to# include "system.h" and <io.h>, then you can use "IOWR(CLOCK_GEN_BASE, 0, x)" to change the divisor to x (where output clock frequency = sysclock / (2 * (x + 1)) ), and "IOWR(CLOCK_GEN_BASE, 0, 0)" to turn it off.

[Altera_Forum]

--- Quote End ---   Hardware, definitely.  If you want a free-running, steady clock signal, you just need a peripheral to generate it. Try this Verilog: ...   --- Quote End ---   Hi Mike, thanks a lot for your advice. I was trying to follow the steps you showed me in previous post. Everything went fine until I started the compilation of my project in Quartus II. Here, in Pre-compilation (or Analysis) phase I get the following error: "" Error: Node instance "the_ClockGenerator" instantiates undefined entity "ClockGenerator" "" Clicking this message takes me into the Verilog design file of the ClockGenerator module. I tried to browse the forum to find any hint, but couldn&#39;t find anything useful.  Do you have any idea how to resolve this problem?

[Altera_Forum]

--- Quote Start ---  originally posted by cableguy@Nov 2 2005, 12:08 PM "" error: node instance "the_clockgenerator" instantiates undefined entity "clockgenerator"  "" clicking this message takes me into the verilog design file of the clockgenerator module. i tried to browse the forum to find any hint, but couldn&#39;t find anything useful.  do you have any idea how to resolve this problem? <div align='right'><{post_snapback}> (index.php?act=findpost&pid=10740)  --- quote end ---    --- Quote End ---    Ah, Things That You Learn About SOPC Builder That They Forgot to Tell You# 1138: Make sure a custom component&#39;s name, the name of any of its instances in the SOPC system, and the names of the design files don&#39;t conflict.  Those names you give the various peripherals in your system? SOPC Builder uses them as module names when it generates your system. So if you write ClockGenerator.v, which contains ClockGenerator, then create a new component, then add one of those to your system and rename its instance to "ClockGenerator" (instead of something else like "clock_gen"), there will be a conflict because SOPC Builder will generate a ClockGenerator module that includes a ClockGenerator module, and Quartus gets confused chasing its own tail, and Falls Down.  Yeah, they should generate a warning when you make that mistake, and prevent system generation, but they don&#39;t. Maybe in a future version. Right after they properly quote all path and filenames in their scripts so that you can have spaces in your pathnames and still expect it to work.  Hope that helps.

[Altera_Forum]

--- Quote Start ---  originally posted by mike desimone@Nov 2 2005, 05:11 PM ah, things that you learn about sopc builder that they forgot to tell you# 1138: make sure a custom component&#39;s name, the name of any of its instances in the sopc system, and the names of the design files don&#39;t conflict.  --- Quote End ---    I created ClockGenerator.v file with your code in module named ClockGenerator. Then I inserted this module in my project in SOPC builder and name the new component SPI_CLK_HW. However, I am still getting the same error...is this what I was supposed to do or haven&#39;t I followed your idea correctly?