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We config the cyclone (EP1C6) successfully using CPLD(EMP3128). (CPLD read from Flash and config FPGA by PS mode, in 3.125MHz like Altera NiosII Kit)
So we just modify a little to config cyclone II(EP2C5), but after CONFIG_DONE=1, the FPGA cannot get into USER_MODE successfully. But the Handbook said it can workup by itself. What's wrong? which things I should take care?Link Copied
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At last , I make it work by DCLK pulled low("0") after CONFIG_DONE='1' while it was high ("1") at first.
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