Questions about CompactFlash Interface

[Altera_Forum]

I downloaded "Compact Flash support for Nios II 5.0" on niosforum website and tried it. But I found it's data transfer rate (read operation) is only 300~400KB/s on my cyclone ep1c20 evaluation board, the CF card is 1GB. There are some questions: 

  (1) Could you please tell me the "Max Data Transfer Rate" of Nios II CF Interface if the clk of nios-II is fixed (such as 50MHz) and the CF card is not the blttleneck?    (2) In your program, what factors can affect the speed of CF interface if theh CF card is not a bottleneck?   (3) Is there any method to improve the data transfer rate of the CF interface, with fixed nios-II clock?   Thanks a lot!

[Altera_Forum]

The following is an email I sent to the poster of this question to address the problem -- posting it here for the benefit of others. 

---  Hello,  Thanks for writing. The reason for the low data transfer rates is not nios clock speed (unless you were running very slowly), but because the controller is very simple, and is designed to work with all compact flash cards (even the slowest cards). In "True IDE" mode, which our controller uses, compact flash cards operate in several "PIO Modes". "PIO Mode 0" is the slowest, and the read/write/wait state timing parameters for our controller are adjusted to work with mode 0 (you can see these in the class.ptf file for the compact flash component).  The PIO mode that a particular CF card supports can be read at runtime in certain registers on the card itself. A more advanced controller might read the status of the CF card when a card is inserted, and then adjust its read/write timing accordingly. Our controller is designed for simplicity, and does not support this feature.   You can read more about the different PIO modes and associated speeds in the compact flash specification (available at www.compactflash.org) -- this specification was used when we created the timing parameters for our compact flash interface.  One suggestion would be that if you are SURE that a certain PIO mode (or faster) will be used (for example, you know that all CF cards that are used in your design will be at least PIO mode 2), you could look at the timing supplied in the compact flash specification document, and then modify the timing values in our controller's class.ptf file. After this, remove the compact flash interface from your design in SOPC Builder, add it back again, and re-generate the system. The Avalon bus fabric generated will now operate more quickly.  Note, however, that this could be dangerous if anyone accidentally uses a slower (older) compact flash card... the timing would not be met, and proper operation would not be guaranteed.  Regards,  Jesse

[Altera_Forum]

Thank you! 

I should have post your answer here yesterday, but my Internet connection to this forum was broken until this morning. So, I&#39;m late, http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

[Altera_Forum]

Its okay -- I am happy that this solved your problem.

[Altera_Forum]

Jesse,  

 Was the CF design created similar to the Custom component design flow? Is the source code (VHDL) available for the compact flash task Logic and register files?   I am working on a design that must support PIO modes 0-3 to enable all cards to be read, and allow for data transfers @ PIO mode 2 or 3. My design concept is to emulate the sandard CF interface to the maximum extent possible. This would allow me to test the design using the example code with a few modifications.   I started designing the task logic, but was hoping I could use the same registers as the standard CF design. I would then add one additional register to allow the software to select the speed. The task logic would handle the interface speed. Only problem is, I really don&#39;t know what all of the registers do. I tried looking at the CF header file, but it only assigns the register offsets. It never really explains The ranges of values, or what they do. Is there an interface description for this?   Any information would be appreciated.   Thanks  Rob Brown http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif     --- Quote Start ---  originally posted by jesse@Nov 17 2005, 04:27 PM the following is an email i sent to the poster of this question to address the problem -- posting it here for the benefit of others. ---  hello,  thanks for writing. the reason for the low data transfer rates is not nios clock speed (unless you were running very slowly), but because the controller is very simple, and is designed to work with all compact flash cards (even the slowest cards). in "true ide" mode, which our controller uses, compact flash cards operate in several "pio modes". "pio mode 0" is the slowest, and the read/write/wait state timing parameters for our controller are adjusted to work with mode 0 (you can see these in the class.ptf file for the compact flash component).  the pio mode that a particular cf card supports can be read at runtime in certain registers on the card itself. a more advanced controller might read the status of the cf card when a card is inserted, and then adjust its read/write timing accordingly. our controller is designed for simplicity, and does not support this feature.   you can read more about the different pio modes and associated speeds in the compact flash specification (available at www.compactflash.org) -- this specification was used when we created the timing parameters for our compact flash interface.  one suggestion would be that if you are sure that a certain pio mode (or faster) will be used (for example, you know that all cf cards that are used in your design will be at least pio mode 2), you could look at the timing supplied in the compact flash specification document, and then modify the timing values in our controller&#39;s class.ptf file. after this, remove the compact flash interface from your design in sopc builder, add it back again, and re-generate the system. the avalon bus fabric generated will now operate more quickly.  note, however, that this could be dangerous if anyone accidentally uses a slower (older) compact flash card... the timing would not be met, and proper operation would not be guaranteed.  regards,  jesse <div align='right'><{post_snapback}> (index.php?act=findpost&pid=11037)  --- quote end ---    --- Quote End ---  

[Altera_Forum]

I am using the Altera CycloneII development board for an FPGA design that incorporates a PCI core and a number of peripheral functions, one of which is an interface to a Compact Flash. 

 I understand that the Compact Flash Expansion Module from Microtronix is compatible with the Santa Cruz header on this board.  Is there available IP in source form (from Microtronix or other ) that I could use to accelerate the CF portion of this design?

[Altera_Forum]

I just looked at the CF spec on CompactFlash.org and compared it to the class.ptf file made some adjustments to the timing in the class.ptf file but I really didn’t see any major improvements http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif what are the Altera recommended timings to run the CF in PIO mode 2 and 3? 

 Also is there something else in the NIOS that would cause long write time?  Thanks Steve