Cyc II Dev. Kit: Read from CFI device via Avalon

Altera_Forum · ‎12-02-2005

I am using the Cyclone II development kit.

I have implemented a small peripheral to read the on-board CFI device (AM29LV128) as an Avalon Master. I then use SOPC builder to connect this to the CFI flash component via an Avalon tri-state bridge.

Simulations appear to be working okay, but can't really tell because the data in the flash is all zeroes in the sim.

When I implement in hardware, it seems to be sorta working, but I don't think I'm properly capturing the "readdata" bus. It's 32-bits, and the CFI device is set to BYTE mode, so, based on the sim, when 'waitrequest' is de-asserted, if I read address 0x00000000, I should get back the contents of 0x00000000 through 0x00000003 (32-bits) on 'readdata' in the form of:

(31 down to 0) is (8-bit data from 0x00000000) & (... from 0x00000001 ) & (... from 0x00000002) & (...from 0x00000003), but it doesn't appear to be working that way.

Can someone please explain what data I should expect on a 32-bit 'readdata' bus when I perform a read operation to the CFI device? (Using the simulator, I can see the Avalon Switch Fabric doing four separate reads to support the byte-mode of the CFI device).

I've also noticed that the lower two address bits are ignored by the switch fabric, which causes 32-bit reads since that's what the CFI device supports.

I'm using the default pin assignments that SOPC builder generates for the CFI device, too.

Please help! I'm so close, but so far!

Thanks,

Jon

Altera_Forum · ‎12-03-2005

Little more info...

I set the .dat file to initialize the flash device upon simulation start. So, now I can see what's going on with real data. It appears that my thinking on how the data bus is filled was correct, but there are some weird things with 'waitrequest'.

It seems that 'waitrequest' in the sim drops low for a <1ns period of time somewhere around 2/3 of the way through the read cycle (according to the sim)... Since I'm capturing data on the falling edge of 'waitrequest', this really hoses me up, especially since 'readdata' is only valid until the next rising clock edge. Then, 'readdata' clears out its upper 8-bits for some reason.

I'm still workin' on it, but any assistance on this would be greatly appreciated. I haven't tried using the flow control signals yet.

Thanks,

Jon