Configuration bombs at power up

Altera_Forum · ‎12-06-2005

I have a working design up and running in Quartus 5.0 SP1. I programmed a couple of boards with the image last week. They have been sitting on my test stand cranking away.

In the mean time, I was in the process of fine tuning and making a few adjustments. I did so using Quartus 5.1. As of this morning, I was happy with the current design and started to load the new image on another board and one of the ones I programmed last week.

After powering up both boards, they just sit there and do nothing, as if they have not been configured. As changes were made, I check them out by downloading the image on the FPGA and not the configuration device. I have had no problems programming and executing my image when it is loaded directly onto the FPGA.

I have looked at the configuration pins on the configuration device. It appears that the FPGA goes into an infinite loop trying to get configured (if Auto-restart configuration after error is selected under assignments).

I can program the FPGA using my USB-blaster, and it works just fine.

I have gone over the assignment settings, and can not find anything that stands out. I got the e-mail from Altera this morning about the Software Critical Issue Advisory. I have installed the patch and still have the same problem.

I am using an EP2C35F672 FPGA with an EPC16 configuration device, Quartus 5.1 SP 0.15.

Altera_Forum · ‎12-06-2005

If I deselect "Generate compressed bitstreams" under the Configuration tab, under Device and Pin Options, I am able to get my FGPA to configure correctly.

There must be an error introduced when compressing the bit stream.

This does require a little more time to configure the FPGA (in the order of few mili-seconds).

Doug

Altera_Forum · ‎12-12-2005

I believe when using the EPC16 config device, you should specify the use of a compressed image in the options for each page in the Convert Programming Files tool. The issue really is that there are 2 different compression schemes, one that is in the FPGA itself (EG. CycloneII / StratixII), and another where the EPC16 itself does the decompression. The option you checked may refer to the first compression scheme which i don't believe is supported in the EPC16 device.

--dalon