JTAG and EP2C8

[Altera_Forum]

Hi guys, 

 my problem is a little off topic, but I hope someone can give me some hints.  We developed a small NIOS II PCB with a EP2C8 208 FPGA. The FPGA is configurable via JTAG and EPCS device. Now we assembled the first pcbs and try to load design into the C2 device. Now me found out that the sof files are not loaded correctly. We test 2 board and they show the same errors.  The JTAG header is close (~1 inch) to the FPGA. The TCK has a 1k PD resistor and a 10p cap to ground. TMS, TDI have 1k PU. The whole connections are wired like in http://www.altera.com/literature/hb/cyc2/cyc2_cii51013.pdf (http://www.altera.com/literature/hb/cyc2/cyc2_cii51013.pdf) , page 62.  For the design and download we use Quartus II 5.1. The integrated programmer can detect the Cyclone II device and says always that the dl is complete but the design don't work. The CONF_DONE pin does not go high after the dl.   Does the quartus II programmer verify if the sof files was transfered correct?  Kind regards revolt

[Altera_Forum]

Hi guys, 

 the problems are found and solved http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif   One big problem was the firewall which blocked the access to the JTAG-Server. Another was the distance of the TCK to the other JTAG signals. Now the routing is done with some wires and it works.  regards revolt