sampling technique

[Altera_Forum]

hi there....i'm a user of nios I , currently my project using this nios requires to obtain data (sample data) every 50 micro seconds. How do i do this ? any idea?

[Altera_Forum]

--- Quote Start ---  originally posted by niceguylow@Dec 10 2005, 08:37 AM hi there....i&#39;m a user of nios i , currently my project using this nios requires to obtain data (sample data) every 50 micro seconds. how do i do this ? any idea? <div align='right'><{post_snapback}> (index.php?act=findpost&pid=11462)  --- quote end ---    --- Quote End ---    There are a couple other things which influence your question:  - What is the system clock speed? - How much data do you want to store <=> acquisition time  Assuming your clock speed is 2 MHz, and you store data every 50 us (20kHz), then you have to wait 100 system clocks before you store data.  So a self loadable down counter can do this, the counter starts with value 99, then counts down to 0 and when it is 0 it has to generate a pulse which does two things: 1: reload the counter to 99 2: store data from an input to memory  So the pulse is active when the counter value equals 0.  Instead of loading the counter with a constant value you can also copy that value form a programmable register. (flexibility).  If you have enough clocks between the sample moments, you can store the data in external memory, or on disk? depends on the total acquitition time....  This is how you can do it, you can do it also with software (timer interrupts) but then sample accuracy might be an issue.

[Altera_Forum]

--- Quote Start ---  originally posted by henkb+dec 10 2005, 06:15 am--><div class='quotetop'>quote (henkb @ dec 10 2005, 06:15 am)</div>  --- quote start ---  <!--quotebegin-niceguylow@Dec 10 2005, 08:37 AM hi there....i&#39;m a user of nios i , currently my project using this nios requires to obtain data (sample data) every 50 micro seconds. how do i do this ? any idea? <div align='right'><{post_snapback}> (index.php?act=findpost&pid=11462)  --- quote end ---    --- Quote End ---    There are a couple other things which influence your question:  - What is the system clock speed? - How much data do you want to store <=> acquisition time  Assuming your clock speed is 2 MHz, and you store data every 50 us (20kHz), then you have to wait 100 system clocks before you store data.  So a self loadable down counter can do this, the counter starts with value 99, then counts down to 0 and when it is 0 it has to generate a pulse which does two things: 1: reload the counter to 99 2: store data from an input to memory  So the pulse is active when the counter value equals 0.  Instead of loading the counter with a constant value you can also copy that value form a programmable register. (flexibility).  If you have enough clocks between the sample moments, you can store the data in external memory, or on disk? depends on the total acquitition time....  This is how you can do it, you can do it also with software (timer interrupts) but then sample accuracy might be an issue. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=11463)</div> [/b]  --- Quote End ---    Hi..  Actually, my projects besides involving sampling, each sampled data is obtain then calculate the duty ratio to generate pwm output , which also means that each generated output is based on the previous sample data. besides that, my frequency uses 33.333 MHz and this system goes continuously. At the same time, the period of the generated pulse with shall be the same with the perios of obtaining samples which is 50us. If i insist on using timer interrupt, would it be possible? Please advise me...  Thanks and regards,  Wayne.

[Altera_Forum]

hi, 

 I would do this in hardware. You can try to do it in sw, to make a good choice if it is possilbe in sw more requirements are necessary, you know them so you can calculate if it is possible to do it in sw and keeping time available on the nios for other tasks if there are any.  regards

[Altera_Forum]

--- Quote Start ---  originally posted by henkb@Dec 12 2005, 08:23 AM hi,  i would do this in hardware. you can try to do it in sw, to make a good choice if it is possilbe in sw more requirements are necessary, you know them so you can calculate if it is possible to do it in sw and keeping time available on the nios for other tasks if there are any.  regards <div align='right'><{post_snapback}> (index.php?act=findpost&pid=11484)  --- quote end ---    --- Quote End ---   Hi henk ,   i tried to do in SW but now i discovered the duty cycles for the interrupt is far more that what is expected... can you please guide me in implementing in the hardware ?

[Altera_Forum]

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  Hi henk ,   i tried to do in SW but now i discovered the duty cycles for the interrupt is far more that what is expected... can you please guide me in implementing in the hardware ?[/b]  --- Quote End ---    Hi Wayne,  hmm, solving this really depends on all your requirements, what you want to achive. I assumed you want to store digital data directly available on input ports of the device (ADC?), it could also be that you use the PWM to find the digital equivalent of the analog value or the data is already digital..... Then there is the question where do you store the data?  Assuming you have N bits digital data and you want to store that with a programmable time distance then it is just a counter and a pulse which could for instance trigger a state machine to store data in memory or maybe the pulse itself is enough to store the data (write pulse on an internal memory). Actually this is just digital design. I assume you are familiar with that, if not then there are many books about VHDL and Verilog and there is the Altera documentation to guide you through that process. For me that goes beyond the scope of this forum, then I would be doing your design work.   Regards,