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We are trying to use a part of a StratixII as a RS232 server :
- 6 uarts, at 9600 baud, are connected to the outside world : actual computers - Data from the 6 uarts are "routed" by a NIOS2 ( at 25Mhz ) to 5 juarts - Data is then displayed by the 6 nios2-terminals ( remote access ) To test the above, a 2nd NIOS2 is configured to generate data to the 6 uarts ( no reverse traffic yet ) The above works OK only if the 2nd NIOS2 is throttled to less than 200 char/sec. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif The 1st NIOS2, which routes the data between the uarts and juarts doesn't seem to be the major problem. There are occassional missing char when the char rate is raised. The more disdurbing problem is the disappearance of all the niso2-terminals http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/mad.gif , with the following error msg : nios2-terminal: exiting due to I/O error communicating with target Note : Failure of the nios2-terminals does not affect the operation in the StratixII. As soon as the nios2-terminals are restarted, data is display, and nios2-terminals vanishes, .... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif This symtum remains with the following variations on the routing-NIOS2 : - for both the reduce/non-reduced drivers - use POSIX open/read/write and use the direct I/O ( the IORD & IOWR macros ). - use POSIX open/read/write one-byte-at a time Vs multBytes read/write ( improves through put ) - for all 6 uarts/juarts Vs only one uart/juart - run nios2-terminal on WinXP and Linux. ( The WinXP nios2-terminals takes a bit more time to crash ) My gut feel is that there is a bandwidth limit on the juart ( through the JTAG/USBBlaster ), and the USBBlaster/HostDriver failed to handle overflow, and cause the JTAG port to be closed. Your insights to improve / explain the implementation is much apprecipated. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/ph34r.gifLink Copied
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You did not say which software are you using on the device... is it the standard Altera HAL?
did you try to use non-blocking writes? what do you use for the communication among the two CPUs? bye Paolo- Mark as New
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--- Quote Start --- originally posted by paolo.gai@Dec 14 2005, 06:37 AM you did not say which software are you using on the device... is it the standard altera hal?
did you try to use non-blocking writes?
what do you use for the communication among the two cpus?
bye
paolo
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--- quote end ---
--- Quote End --- I am prototyping with the StratixII (DSP) evalboard, and stock drivers/libs are used. The data flow ( unidirectional for now ) : 2nd Nios2 -> UARTs -> UARTs -> Routing Nios2 -> JUARTs -> nios2-terminals There is no commuication between the NIOS2s All read/write by the "Routing Nios2" to the juarts/uarts are non-blocking. Read/write by the "2nd Nios2" are blocking calls.
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