PCI in uClinux

[Altera_Forum]

Does suported PCI in uClinux for NIOS II with Altera PCI Compiler 4.0 pci_mt_32 megafuntion ? 

Anywho uses this options ?  I can&#39;t compile kernel with PCI support...    http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif   Thnx...

[Altera_Forum]

there is no support for PCI Cores yet

[Altera_Forum]

I will post the driver for altera pci host bridge soon.

[Altera_Forum]

Hippo, 

   --- Quote Start ---  originally posted by hippo@Mar 14 2006, 08:18 PM i will post the driver for altera pci host bridge soon.  --- Quote End ---    Will that include the configuration stage as well?  And, how far are you? One of my customers is dying to see this. I&#39;m perfectly willing to do a bit of work on this one, by the way.  Best regards,    Ben

[Altera_Forum]

--- Quote Start ---  originally posted by bentwy+apr 21 2006, 08:02 pm--><div class='quotetop'>quote (bentwy @ apr 21 2006, 08:02 pm)</div>  --- quote start ---  hippo,  <!--quotebegin-hippo@Mar 14 2006, 08:18 PM i will post the driver for altera pci host bridge soon.  --- Quote End ---    Will that include the configuration stage as well?  And, how far are you? One of my customers is dying to see this. I&#39;m perfectly willing to do a bit of work on this one, by the way.  Best regards,    Ben <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14552)</div> [/b]  --- Quote End ---   please check step17 in this thread, http://forum.niosforum.com/forum/index.php?showtopic=3174 (http://forum.niosforum.com/forum/index.php?showtopic=3174)  The PCI config is included.

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

--- Quote Start ---  originally posted by bigboss25+apr 24 2006, 06:53 pm--><div class='quotetop'>quote (bigboss25 @ apr 24 2006, 06:53 pm)</div>  --- quote start ---    --- quote start ---  originally posted by hippo@apr 22 2006, 10:03 am   --- quote start ---  originally posted by bentwy@apr 21 2006, 08:02 pm hippo,  <!--quotebegin-hippo@Mar 14 2006, 08:18 PM i will post the driver for altera pci host bridge soon.  --- Quote End ---    Will that include the configuration stage as well?  And, how far are you? One of my customers is dying to see this. I&#39;m perfectly willing to do a bit of work on this one, by the way.  Best regards,    Ben <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14552)</div> [/b]  --- Quote End ---   please check step17 in this thread, http://forum.niosforum.com/forum/index.php?showtopic=3174 (http://forum.niosforum.com/forum/index.php?showtopic=3174)  The PCI config is included. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14564)</div> [/b]  --- Quote End ---   Hippo, do you mean that your driver will be written for Altera PCI Compiler 4.0 pci_mt_32 megafuntion ? <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14597)</div> [/b]  --- Quote End ---   Yes, it is. I had the altera pci core in host bridge mode working on my boards.

[Altera_Forum]

Hi, 

i have a custom board with the Altera PCI Compiler PCI Core in Host-Bridge-Mode and one Gigabit Ethernet Controller connected to the Bridge. The Gigabit Ethernet Controller ist the Intel RC82540EM Ethernet Chip with Legal-PCI Bus.  I have fixed the ALTPCI.C-File and the Kernel detects the Ethernet Chip.  The Kernel says: *******************snipp******************************************* Autoconfig PCI channel 0x02157bd8 Scanning bus 00, I/O 0x86300000:0x86400000, Mem 0x86100000:0x86200000 00:01.0 Class 0200: 8086:100e (rev 02)  Mem at 0x86100000   I/O at 0x86300000  map slot 1 pin 1 irq 15 Setting IRQ for slot 0000:00:01.0 to 15 *******************Snapp*******************************************  As you see, the Intel Chip(Vendor 8086, Device 100E, Revision 2) was found on the PCI Bus. So i think the Bus-Hardware works fine... The Ethernetchip then is attached to the Avalon-Addressspace and i can read and write the Configuration Space of the Ethernet Chip. (PCI-Base is 0x8600000, The Ethernetchip Configuration is then at 0x8600800). I can read and write it without problems.... But then, when the driver of the Ethernetchip (/NET/E1000) wants to setup the Ethernet Controller the Kernel says:  *******************snipp******************************************* Intel® PRO/1000 Network Driver - version 6.3.9-k4 Copyright © 1999-2005 Intel Corporation. ID: 34986200 PCI: Enable Device PCI: Device is enabled... e1000: 0000:00:01.0: e1000_probe: The EEPROM Checksum Is Not Valid e1000: probe of 0000:00:01.0 failed with error -5 *******************Snapp*******************************************  The EeProm is programmed orrectly. But the Ethernetcontroller is not accessible over the Mem-Mapped Adress 0x86100000. The driver wants to access the first Control-Register at this address.... Wenn i read (with INL()) the Adresses i get: *******************snipp******************************************* Adresse: 0x86100000 Data: 0x100000 Adresse: 0x86100004 Data: 0x100004 Adresse: 0x86100008 Data: 0x100008 Adresse: 0x8610000c Data: 0x10000c Adresse: 0x86100010 Data: 0x100010 Adresse: 0x86100014 Data: 0x100014 Adresse: 0x86100018 Data: 0x100018 Adresse: 0x8610001c Data: 0x10001c Adresse: 0x86100020 Data: 0x100020 Adresse: 0x86100024 Data: 0x100024 Adresse: 0x86100028 Data: 0x100028 Adresse: 0x8610002c Data: 0x10002c Adresse: 0x86100030 Data: 0x100030 Adresse: 0x86100034 Data: 0x100034 Adresse: 0x86100038 Data: 0x100038 Adresse: 0x8610003c Data: 0x10003c *******************Snapp*******************************************  What is this? Anyone ideas? When i try to access the Controller over the I/O-Mapped-Space i get only the result 0x04 .... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif   I hope anyone can help me....  Thankx Marco

[Altera_Forum]

Up.. 

Maybe someone has Ideas?  Thanx Marco

[Altera_Forum]

It looks like that the chip does not repsonse to memory acces. 

So the access timeout.  Please use scope or LA, to look at pci bus lines, frame, irdy, trdy , ad[]. within a short pci memory registers access loop.  Check the altera pci core config page 4.  Try config the e1000 to a lower memory address in pci mmemory space, and check the memory access.

[Altera_Forum]

You have to update altera pci core config page 4, avalon config, 

change the pci base address of 32 bits memory page, to the value of avalon bus address assigned in sopc builder. ie, 86100000 in your case . you should also update the io page mapping.  We want to use the same address mapping in both pci space and avalon space.  config space , pci base 0 , == avalon 86000000 mem space, pci base 86100000, == avalon 86100000 unused space? io space, pci base 86300000, == avalon 86300000

[Altera_Forum]

--- Quote Start ---  originally posted by hippo@Sep 25 2006, 11:48 PM it looks like that the chip does not repsonse to memory acces. so the access timeout.  please use scope or la, to look at pci bus lines, frame, irdy, trdy , ad[]. within a short pci memory registers access loop.  check the altera pci core config page 4.  try config the e1000 to a lower memory address in pci mmemory space, and check the memory access. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18447)  --- quote end ---    --- Quote End ---    If you do not have access to a LA or don&#39;t want to connect a lot of wire (a bit boring http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/dry.gif ), a good choice is to use SignalTap II Logic Analyzer which is included with Quartus. You will have to recompile your design, and of course SignalTap II IP will need some extra LE.  You must also have a full Quartus license in order to use SignalTap II, or with the Quartus Web Edition you must enable &#39;Talkback feature&#39;, althought I&#39;m not sure.  Hope this will help. Regards.

[Altera_Forum]

Hi Hippo, Hi Bigboss 

 Thanx for your answers...  i have now logged the PCI Bus DATA-READ (BE = 0x06h). Here is a plot from the SignalTap trace: trace-picture (http://www.mabcom.de/pci.jpg)  Maybe something wrong? My Software gives a 0x32bfffff when read from Adress 0x200000. In the Signaltap you see another value. Why?  Any ideas? What about the PCI clk? I have clocked the Signaltap Analyser with PCI_CLK. I generate a 33MHz CLK and give it to CLK_PCI_COMPILER input clk and also the same clock to the Hardware PCI_CLK_Pin. I have also added Phase-Shifting, but that doesn&#39;t work.  I hope you can help me http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif   Bye Marco

[Altera_Forum]

Hi Marco, 

 There are no active devsel nor trdy. So the e1000 is not responding to memory access. The ad bus is floating, and the value is meaningless.  Can you give your sopc ptf and altpci.c ? I will check the translation table.  The PCI clock might be OK, since you can access the config space.

[Altera_Forum]

Hi Hippo, 

 The System PTF File you can find here (http://www.mabcom.de/std_2s60.ptf)  The altpci.c-File you can find here (http://www.mabcom.de/altpci.c)  I hope you can find anything http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif   Thanx Marco     --- Quote Start ---  originally posted by hippo@Sep 26 2006, 11:24 PM hi marco,  there are no active devsel nor trdy. so the e1000 is not responding to memory access. the ad bus is floating, and the value is meaningless.  can you give your sopc ptf and altpci.c ? i will check the translation table.  the pci clock might be ok, since you can access the config space. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18458)  --- quote end ---    --- Quote End ---  

[Altera_Forum]

I Have found out another funny thing. 

The Altera PCI Bridge has PCI-Bus Access at 0x060000000.  On Page 4 from Setup Offset 0x0000000 is Config, 0x00100000 is Mem and so on. So, when the System accesses the PCI-Bus it writes a 0x86100000 for Mem in the PCI-Bar, but the physical Bus Access is to Address 0x100000. So the PCI-Device doesn&#39;t answer. It&#39;s not the same address. I have patched the Linux kernel to mask out the highest bit. And i have told the PCI-Bridge-Setup to map the Mem to 0x061000000. Now the access is ok. I can read the Config-Register with Memory Access. But when the Ethernet-Driover wants to access the device it doesn&#39;t work. Please see here a Memory Access Trace: mem_trace (http://www.mabcom.de/memtrace1.jpg)  As you see, the DEVSEL goies Low, also the TRDY, but why so late? Does the Master abort the transfer? And why are there hundreds off accesses to the same Address?   Thanx Marco

[Altera_Forum]

Hi Marco, 

 When I perpared the altpci driver, I had tried to simplify the address translation between pci space and avalon space. I decided to use the same address mapping for both spaces, so that I don&#39;t have to add another address tables in drivers.  I checked your ptf and altpci.c . Please update in the pci core toolbench, page 4, avalon config. change the pci base address in the address translation table,  row 0, pci config space, pci base 0, == avalon 0x06000000 uncached to nios2 0x86000000 row 1, pci mem space, pci base 0x86100000, == nios2 0x86100000 row 2, pci mem space, pci base 0x86200000, == nios2 0x86200000 .... row 7, pci io space, pci base 0x86700000, == nios2 0x86700000  Note, we need to uncache the access for nios2, by setting address bit 31 .  Hope this will help.  Hippo

[Altera_Forum]

Hi Hippo, 

 PCI problems solved. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif  GigaBit Ethernet works fine with uClinux http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif   But your last tip doesn&#39;t work. The PCI-Compiler doesn&#39;t accept the highest Bit set.  To get PCI for me to work i just masked out the highest bit in the Device Bar Setup in ALTPCI.C I wondered why you haven&#39;t done it. I think PCI can&#39;t work without that. Or just I/O-Access is possible.  Solong, i have a cheap and well working Gigabit-Ethernet on my uClinux-Board. Tomorrow i will make a performance test. The results i will post here.  Thanx and Bye Marco    --- Quote Start ---  originally posted by hippo@Sep 27 2006, 11:33 PM hi marco,  when i perpared the altpci driver, i had tried to simplify the address translation between pci space and avalon space. i decided to use the same address mapping for both spaces, so that i don&#39;t have to add another address tables in drivers.  i checked your ptf and altpci.c . please update in the pci core toolbench, page 4, avalon config. change the pci base address in the address translation table,  row 0,  pci config space, pci base 0, == avalon 0x06000000 uncached to nios2 0x86000000 row 1, pci mem space, pci base 0x86100000, == nios2 0x86100000 row 2, pci mem space, pci base 0x86200000, == nios2 0x86200000 .... row 7, pci io space, pci base 0x86700000, == nios2 0x86700000  note, we need to uncache the access for nios2, by setting address bit 31 .  hope this will help.  hippo <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18476)  --- quote end ---    --- Quote End ---    http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif

[Altera_Forum]

Hi Hippo, 

 how fast is the PCI implementation? Does it works with DMA? I think it&#39;s a little bit slowly when i test the PCI Performance with Giga-Ethernet.  I think the Linux TCP-IP-Stack doesn&#39;t use the PCI-Memory Access.  Can we solve it quickly?  Thanx Marco

[Altera_Forum]

--- Quote Start ---  originally posted by mabcom@Sep 29 2006, 01:45 AM hi hippo,  how fast is the pci implementation? does it works with dma? i think it&#39;s a little bit slowly when i test the pci performance with giga-ethernet.  i think the linux tcp-ip-stack doesn&#39;t use the pci-memory access.  can we solve it quickly?  thanx marco <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18494)  --- quote end ---    --- Quote End ---   Hi MadCom, would it be possible for you to create on "how-to" on Nios Wiki, explaining what you did (hardware, Ip cores used... and of course uClinux driver). I think it would help a lot of people.  Thanx. Regards.

[Altera_Forum]

Hi, 

 i have now tested a little bit.  To Hippo: DMA works. The PCI accesses the SDRAM via Master-Access.  The maximum speed i reached with a Nios/f @100MHz, and CAS2/SDRAM@100MHz is:  47Mbit/s for TCP and 49Mbit/s for UDP. I think the Nios is not able to give more....  These are values under uClinux. Therefore the are not too bad, i think. But the best thing is, that PCI works. So really everything can be combined with uClinux (Wlan, MiniPCI, SCSI and so on...)  To Bigboss25: I will write a NiosWiki Article soon about that.  Solong Marco      --- Quote Start ---  originally posted by bigboss25+sep 29 2006, 02:15 am--><div class='quotetop'>quote (bigboss25 @ sep 29 2006, 02:15 am)</div>  --- quote start ---  <!--quotebegin-mabcom@Sep 29 2006, 01:45 AM hi hippo,  how fast is the pci implementation? does it works with dma? i think it&#39;s a little bit slowly when i test the pci performance with giga-ethernet.  i think the linux tcp-ip-stack doesn&#39;t use the pci-memory access.  can we solve it quickly?  thanx marco <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18494)  --- quote end ---    --- Quote End ---   Hi MadCom, would it be possible for you to create on "how-to" on Nios Wiki, explaining what you did (hardware, Ip cores used... and of course uClinux driver). I think it would help a lot of people.  Thanx. Regards. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18495)</div> [/b]  --- Quote End ---