SDRAM and speed gain

[Altera_Forum]

I want to build a system using SOPC builder that contains a SDRAM controller, that is accessed from a NIOS2 and a DMA controller, both running at 50MHz. If I have the SDRAM controller run at 100MHz, will this give me a speed gain, because memory access might be faster or will it slow things down because of logic needed for clock domain crossing? 

  On a completely unrelated note: Has somebody used a quartz other than the 50MHz one the cyclone dev-kit ships with on one of these boards? What are your experiences?

[Altera_Forum]

It's hard to say whether it will be any faster or not. In general, the SDRAM controller isn't efficient, so adding domain-crossing logic probably will not help you out much. IT shouldn't be hard to run a simple test that reads all the locations and measures the timeusing a timer.

[Altera_Forum]

--- Quote Start ---  originally posted by kalle leo@Mar 16 2006, 06:52 AM i want to build a system using sopc builder that contains a sdram controller, that is accessed from a nios2 and a dma controller, both running at 50mhz. if i have the sdram controller run at 100mhz, will this give me a speed gain, because memory access might be faster or will it slow things down because of logic needed for clock domain crossing?   on a completely unrelated note: has somebody used a quartz other than the 50mhz one the cyclone dev-kit ships with on one of these boards? what are your experiences? <div align='right'><{post_snapback}> (index.php?act=findpost&pid=13502)  --- quote end ---    --- Quote End ---    From experience I can guarantee that it will be slower due to the clock domain crossing. It takes several clock cycles for the clock synchronization modules to pass data. This has to occur both on the reads and the writes. You would be better off to avoid the clock synchronization modules. I&#39;m not sure what FPGA you are using but typically you use a PLL to bump up the frequency. You don&#39;t really want to replace the crystal unless that is your only alternative. If you do, make sure you look at the board schematics for your development board and that your replacement crystal will work with the rest of the oscillation circuit (capacitors or resistors usually).

[Altera_Forum]

Excuse sirs, 

let me make use of this question to take some doubts out. I didin&#39;t understand well the reply from jakos, so sorry if I&#39;m being redundant.  I use a 50Mhz Nios II Board Cyclone II. If I use PLLs in my Quartus projects can I improve the speed of my application? (For example wether I change the clock speed of all componentes (Nios II processor, extern memories,..) to 100Mhz). Was it what you mean, jakob?  Thanks, Mendonca

[Altera_Forum]

Yes. The purpose of a PLL is to take one clock signal (like the 50MHz signal on the development board) and produce another clock signal. With the produced output signal, you have the option of changing the frequency, phase, and jitter characteristics. So you instantiate a PLL in your firmware design. Provide the 50MHz clock as an input. Set the PLL to double the clock frequency to 100MHz. Then provide the 100MHz signal as the input to your SOPC system. So there is really no reason to change the crystal on your development board. The cyclone II on your board has 4 PLLs in it. 

Then you can run your processor and SDRAM at the 100MHz clock without crossing clock domains. You can also provide more than one output clock from the PLL with different frequencies.   Now a second concern is timing. 100MHz is not very fast so you really shouldn&#39;t have problems running at this speed. Once you recompile the firmware project in Quartus the timing analyzer will tell you whether you are meeting timing requirements or not.  Hope this helps. If you have some more specific questions, let me know.

[Altera_Forum]

As the SDRAM controlller does not offer a Clock out for sdram,We need to generate the clock By PLL and make connection to sdram clock input pin, my question is: How can the Data synchronous wiht clock?can i make system clock for nios and sdram clock with different frequence?example sdram clock at 100M but nios system clock in is 50M...

[Altera_Forum]

--- Quote Start ---  originally posted by alon2005@May 21 2006, 10:01 PM as the sdram controlller does not offer a clock out for sdram,we need to generate the clock by pll and make connection to sdram clock input pin, my question is: how can the data synchronous wiht clock?can i make system clock for nios and sdram clock with different frequence?example sdram clock at 100m but nios system clock in is 50m...  <div align='right'><{post_snapback}> (index.php?act=findpost&pid=15487)  --- quote end ---    --- Quote End ---    This has been discussed several times here.  You need 1 clock input that feeds the pll. the pll creates 2 clock output signals. let&#39;s assume c0 is the nios2 core clock and c2 the external sdram clock output. with the pll you have the possability to tune the sdram in order to get the sdram clock synchron with the fpga signals that feed your sdram (phaseshift) you should calculate the phase shift as mentioned by the altera AN??? very easy. now you can have c0 and c2 running at a different clock speed as your clock input. lets assume clock input is 50MHz. you could have c0 with 75MHz and C2 with 100MHz with phase shift. But be aware of that if you have different clock domains inside your fpga you will need clock domain crossing circuits. i doubt that running the core at a different clock speed (in your case 50MHz) as the sdram at 100MHz will lead to a faster system than having both of them running at 50MHz as the clock domain takes a couple of clocks to synchronise. i personaly tune the pll output in a way that both clock outputs (c0 for nios core and all sopc modules, also c2 for external sdram) have the same clock speed but the speed is faster than the external clock speed. in other words, external 50MHz internal >50MHz  regarding your question about synchronize the data .. that is handled by quartus. you just need to tune the pll phase shift as calculated.  It works perfect believe me :-)

[Altera_Forum]

Using other oscillators on the altera demo boards is not only possible, but in some cases even neccessary. In my case, I had to generate a clock frequency of 52428800 Hz to synchronize to external events with a given precision. This is impossible to do with a PLL fed by 50 MHz. So I changed the onboard oscillator to one with a frequency of 32.768 MHz, set the PLL multiplier to 8/5 and got the desired output frequency. 

 The only thing you have to be aware of, is that the altera boards (in my case the NIOS Stratix Dev. Kit) demand an oscillator running at a voltage of 5V. If your oscillator is a 3 Volt type, you need some glue parts. Contact your hardware guy to help you out, if you don&#39;t know what i mean...  Klaus

[Altera_Forum]

--- Quote Start ---  originally posted by jakobjones@May 19 2006, 09:48 PM   now a second concern is timing. 100mhz is not very fast so you really shouldn&#39;t have problems running at this speed. once you recompile the firmware project in quartus the timing analyzer will tell you whether you are meeting timing requirements or not. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=15476)  --- quote end ---    --- Quote End ---   When the timing requirements are not met, the only choice I have is to reduce clock time in SOPC Bulider and regenerate the system? Are there another options in Quartus which can help reach the requirements?  What could be possible causes to the system not meet timing requirements?  If these questions were already discussed, please could someone send me the link? Thanks.

[Altera_Forum]

When Quartus compiles a project it does several things. The first is to look through all the HDL source code that you wrote or that was generated by the SOPC builder and extract the Hierarchy for your design. In other words it&#39;s discovering what design entities are used in your design and what source code files they are located in.  

It then synthesizes the source code meaning it compiles it to a netlist of primitive gates.  The fitter takes this netlist and decides where everything should be placed physically inside the FPGA. This is where the timing comes in. Suppose there are two registers in your design somewhere. They run at a 10ns clock (100MHz) and the one register latches the output data from the other register. Well if the fitter places these two registers too far apart from each other, then it may take longer than 10ns for the output data of the one register to reach the input of the other register. This is a timing violation and the timing analyzer will report this at the end of compilation.  Now fixing these problems is another issue. I&#39;m going to assume that you&#39;re having trouble meeting timing on something that SOPC builder generated and not your own HDL code. If it were your code then you would want to look at the violated timing paths and change your HDL code to improve timing. However, tweaking your SOPC system can have a huge impact on your timing. But if you simply can&#39;t tweak your system then we&#39;ll instead look at some of the fitter options that you can set to help the fitter make timing.   One thing you could do is run the timing optimization advisor. I think in Quartus 5.1 it was located under the tools menu. I&#39;m using Quartus 6.0 now so I don&#39;t remember. This will kind of guide you through things you can do to improve timing. However, a lot of its recommendations will cause your compile time to skyrocket. If you don&#39;t want to run the timing advisor then you can try tweaking some settings on your own. In Quartus, click on the Assignments->Settings menu. Then in the left pane click on the Fitter Settings. Here is where you can change some of the fitter options. Click on the More Settings button to find even more options.  This post has gotten long so you&#39;ll have to take it from here. If you have more specific questions, feel free to post them. It&#39;s very difficult to cover the topic of making timing in a forum post. That&#39;s what Electrical Engineers get paid to do.