Assignements CFI_Flash

[Altera_Forum]

Hi,  

I am working on a Stratix GX Development board. There are 2 FPGAs, one Stratix and one Stratix GX.  The flash memory (S29JL064H) is a Spansion and connected to the Stratix. (22 bit of adress, 16 bit of data)  I have created my Nios with SOPC Builder 5.1.  There is : - a cpu - a tri_state_bridge - jtag_uart - cfi_flash (Custom with 22 bit of adress and 16 bit of data because Spansion family is not mentioned) - onchip_memory  With Quartus 5.1, when I want to assign the pins, I have : Input:  - clk - reset_n  Output:  select_n_to_the_cfi_flash tri_state_bridge_address[22..0] tri_state_bridge_data[15..0] tri_state_bridge_readn write_n_to_the_cfi_flash  I join the pins assignements of the CFI Flash of the documentation: Signal Name Pin Number Stratix Pin Number FLASH_A0 AD31 FLASH_A1 AD32 .... ... FLASH_A21 AC29  FLASH_D0 AF25 FLASH_D1 AF26 ... ... FLASH_D15 AC25  FLASH_RESETn AA25 FLASH_BYTEn Y24 FLASH_CEN AA26 FLASH_OEN AB27 FLASH_WEN AA27  My questions are :  - why the tri_state_bridge_address[22..0] (23 bits instead of my 22 bits) ?  To which pins I must connect: - select_n_to_the_cfi_flash - tri_state_bridge_readn - select_n_to_the_cfi_flash  Thanks for your help.

[Altera_Forum]

select_n_to_the_cfi_flash FLASH_CEN AA26 

tri_state_bridge_address[22..0] tri_state_bridge_data[15..0] tri_state_bridge_readn FLASH_OEN AB27 write_n_to_the_cfi_flash FLASH_WEN AA27  Avalon bus don't use tri-state signals inside the FPGA. The CFI flash must be attached to a tri-state avalon bridge.  The GX chip has the DDR sdram. You should try Nios2 uClinux on GX first. Use sopc build to creat the chip, 1. nios2 fast core with jtag debug 2. timer 3. jtag uart 4. DDR sdram, you must assign correct pin out to DDR chip.  5. tri-state bridge (dummy) 6. cfi flash (dummy)  save a copy of the ptf with 1-6 for kernel hwselect.  remove 5-6, generate hardware , compile in quartus II to get the sof. Then you can follow buildroot guide to build kernel zImage and try out.