Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++

Edge Capture

Altera_Forum
Honored Contributor II
1,213 Views

I'm using PIO cores to change informations among processors. When I send some data from a cpu A to a cpu B, A also sends a flag signal to B. In B, its input PIO (which receives that signal) is sensitive to either rising or falling edge. However, every time A sends data to B, it needs to toggle the value of flag (between 0 and 1) in order to B capture some edge. 

I'd like to avoid these "toggles" (my application has 4 flags till now). Is there some another way (another PIO resource) to give notice B that a new data is avaliable to it? 

 

Another thing: If I use intensively internal Pio Cores can I have problems with the Watchdog time? Which ones? (As far I can see the pio cores use the Avalon Switch Fabric.) 

 

Thanks people!!!
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
290 Views

 

--- Quote Start ---  

originally posted by mendonca@May 30 2006, 08:18 PM 

i'm using pio cores to change informations among processors. when i send some data from a cpu a to a cpu b, a also sends a flag signal to b. in b, its input pio (which receives that signal) is sensitive to either rising or falling edge. however, every time a sends data to b, it needs to toggle the value of flag (between 0 and 1) in order to b capture some edge. 

i'd like to avoid these "toggles" (my application has 4 flags till now). is there some another way (another pio resource) to give notice b that a new data is avaliable to it? 

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=15695) 

--- quote end ---  

 

--- Quote End ---  

 

 

When you mean "sensitive to either rising or falling edge" you mean you&#39;ll raise a remote interrupt for every data you are sending to the other CPU?  

 

 

--- Quote Start ---  

originally posted by mendonca@May 30 2006, 08:18 PM 

another thing: if i use intensively internal pio cores can i have problems with the watchdog time? which ones? (as far i can see the pio cores use the avalon switch fabric.) 

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=15695) 

--- quote end ---  

 

--- Quote End ---  

 

 

I don&#39;t think you&#39;ll have such problems... the Avalon is basically a crossbar switch! 

 

bye 

 

Paolo
0 Kudos
Altera_Forum
Honored Contributor II
290 Views

 

--- Quote Start ---  

originally posted by paolo.gai@Jun 3 2006, 05:24 PM 

when you mean "sensitive to either rising or falling edge" you mean you&#39;ll raise a remote interrupt for every data you are sending to the other cpu?  

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=15695) 

--- quote end ---  

 

--- Quote End ---  

 

 

Yes. Every time I send data (a new data) to another cpu, this one may be warned. I&#39;ll run a iterative algorithm on the system. 

 

 

--- Quote Start ---  

originally posted by paolo.gai@Jun 3 2006, 05:24 PM 

i don&#39;t think you&#39;ll have such problems... the avalon is basically a crossbar switch! 

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=15844) 

--- quote end ---  

 

--- Quote End ---  

 

 

Thanks!
0 Kudos
Reply