Audio Codec on CycloneII DSP Kit

Altera_Forum · ‎07-07-2006

I have a CycloneII DSP Development kit and want to write data to the TI TLV320 audio codec chip on the board. I don't see an existing way to do that with the original full feature design. I try adding an SPI component (master) with the SOPC builder, generate, update the full_2C35 component in Quartus II. At this point I need help to answer a couple of questions before compiling.

1. My first problem is how to connect the SPI signals to pins? I can find the pin numbers for the TLV320 device from the DSP kit reference manual, but how do I assign them to the signals on the project diagram? Please explain, or point me to the documentation that tells me, how to get new pin assigments to appear on the diagram.

2. The next problem is what should I connect the MISO_to_the_spi to? I'm I right in thinking that want to connect MOSI_from_the_spi to AUDIO_SDIN, SCLK_from_the_spi to AUDIO_SCLK, and SS_n_from_the_spi to AUDIO_CSN?

Thanks for any helps, pointers, or suggestions.

Dave

Altera_Forum · ‎07-12-2006

1) Assuming you know which pins on your FPGA connect to the TLV320 device, you use the Assignment Editor: http://www.altera.com/literature/hb/qts/qts_qii52013.pdf (http://www.altera.com/literature/hb/qts/qts_qii52013.pdf). If you don't know what pins to assign I would take a look at the documentation/schematics for that board to find out which FPGA pins need assigning.

Assignment Editor will add your pin mapping to the <project>.qsf file in your project folder. You can jump directly to this assignment as well if you right click the pin in the schematic and select locate in the assignment editor (sorry I don't have Quartus II installed on this machine to check the exact name).

2) SPI is made up of four signals:

MISO - Master In Slave Out (Rx from the master's point of view)

MOSI - Master Out Slave In (Tx from the master's point of view)

SCLK - Serial clock

SS_N - Slave Select (in this case active low)

So a SPI master component will drive out MOSI, SCLK, and SS_N. The SPI master component will take in MISO. I'm not familar with the chip you are using but your wiring sounds right to me.

Also as a side note make sure to check the audio codec data sheet since you will need to make sure you meet the timing specification for the device. SPI has two phase and two polarity options so there are 4 combinations (see the SPI documentation to learn more). Some SPI devices also need a delay between the assertion of slave select and when the serial clock starts (in the SOPC Builder component this is called "specific delay"). Last but not least you need to pick a serial clock and data width that matches what the component expects.

I hope that helps.

Altera_Forum · ‎07-14-2006

Thank you, BadOmen, for your help! I can now talk to the audio codec control interface using SPI. Now I need to talk to the data interface referred to as the digital audio interface in the TLV320AIC23B spec. in order to send (or receive) audio data to be played (or captured).

Does anyone know of any Altera examples that interface to the TI AIC23b audio codec? I'm thinking of using a lpm_shiftreg, but then I still need to get the clocks and other signals synchronized. The codec has 4 different modes for its digital audio interface - right justified, left justified, I2S, and DSP mode. The DSP mode is "compatible with the McBSP ports of TI DSPs." Does anyone know of a McDSP component that I can drop into my Cyclone II part? I'm open to any other suggestions.

Regards,

Dave